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s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 32 - b it arm ? cortex ? fm0+ based microcontroller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 05091 rev.*a revised february 10, 2016 the s6e1a1 series is a series of highly integrated 32 - bit microcontrollers designed for embedded controllers aiming at low power consumption and low cost . th is s eries has the arm cortex - m0+ processor with on - chip flash memory and sram, and consists of peripheral functions such as various t imers, adcs and c ommunication i nterfaces (uart, c sio, i2c , lin ). the products which are described in this data sheet are placed into typ e 1 - m0+ product categories in "fm 0+ family peripheral manual". f eatures 32 - bit arm cortex - m0+ core ? processor version: r0p1 ? maximum operating frequency: 40 mhz ? nes ted vectored interrupt controller (nvic): 1 nmi (non - maskable interrupt) and 32 peripheral interrupt with 4 selectable interrupt priority levels ? 24 - bit system timer (sys tick): system timer for os task management bit band operation compatible with cortex - m 3 bit band operation on - c hip memories ? flash memory ? up to 88 kbyte ? read cycle: 0 wait - cycle ? security function for code protection ? sram th e on - chip sram of this series has o ne independent sram . ? sram : 6 kbyte multi - function s erial i nterface (max 3 channels ) ? 128 bytes with fifo in all channels ( t he number of fifo ste ps varies depending on the settings of the communication mode or bit length.) ? the operation mode of each channel can be selected from one of the following. ? uart ? csio ? lin ? i 2 c ? uart ? full duplex double bu ffer ? parity can be enabled or disable d . ? built - in dedicated baud rate generator ? external clock available as a serial clock ? various error detection functions (parity errors, framing errors, and overrun errors) ? csio ? full duplex double buffer ? built - in dedicated baud rate generator ? overrun error detection function ? serial chip select function (ch.1 and ch.3 only) ? data length : 5 to 16 bit s ? lin ? lin protocol rev.2.1 supported ? full duplex double buffer ? master/slave mode supported ? lin break field generat ion function ( the length is variable between 13 bits and 16 bits. ) ? lin break delimiter generation function ( the length is variable between 1 bit and 4 bits. ) ? various error detect ion functions available (parity errors, framing errors, and overrun errors) ? i 2 c ? st andard - mode (max : 100 kbps) supported / fast - mode (max 400kbps) supported . dma controller ( 2 channels) the dma controller has its own bus independent of the cpu , and cpu and dma controller can process simultaneously. ? 2 independently configur able and operable channels ? it can start a transfer with a software request or a request from a built - in peripheral. ? transfer address area: 32 bit s (4 gbyte) ? transfer mode: b lock transfer/ b urst transfer/ d emand transfer ? transfer data type: byte/halfword/word ? transfer block count: 1 to 16 ? number of transfers: 1 to 65536
document number: 002 - 05091 rev.*a page 2 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a a/d converter (max : 8 channels ) ? 12 - bit a/d converter ? successive a pproximation type ? conversion time : 0.8 s @ 5 v (s6e1a1xc0a) / 2.0 s (s6e1a1xb0a) ? priority conversion available ( 2 levels of priority) ? scan conversion mode ? built - in fifo for conversion data storage (for scan conversion: 16 steps, for p riority conversion: 4 steps) base timer (max : 4 channels) the operation mode of each channel can be selected from one of the following . ? 16 - bit pwm timer ? 16 - bit ppg timer ? 16/32 - bit reload timer ? 16/32 - bit pwc timer general - p urpose i/o port this series can use its pin as a general - purpose i/o port when it is not used for an external bus or a peripheral function. all ports can be set to fast general - purpose i/o ports or slow general - purpose i/o ports. in addition, this series has a port relocate function that can set to which i/o port a peripheral function ca n be allocated. ? all ports are fast gpio which can be acc essed by 1cycle ? capable of controlling the pull - up of each pin ? capable of reading pin level directly ? p ort relocate function ? up to 37 fast general - purpose i/o p orts @48pin p ackage ? certain ports are 5 v tolerant. s ee " 3 . p in a ssignment " and " 5 . i/o c ircuit t ype " for details of such pins. dual timer (32/16 - bit down counter) the dual timer consists of two programmable 32/16 - bit down counters. the operation mode of each timer channel can be selected from one of the following. ? free - run ning mode ? periodic mode (= reload mode ) ? one - shot mode qua drature position/revolutio n c ounter (qp rc) the quadrature position/revolution counter (qprc) is used to me asure the position of the position encoder . in addition, it can be used as an up/down counter . ? the detection edge for the three external event input pins ain, bin and zin is configurable. ? 16 - bit position counter ? 16 - bit revolution counter ? two 16 - bit compare registers multi - function t imer the m ulti - function t imer consists of the following blocks. ? 16 - bit free - run timer 3 ch annels ? input capture 4 ch annels ? output compare 6 ch annels ? a dc start compare 6 ch annel ? waveform generator 3 ch annels ? 16 - bit ppg timer 3 ch annels igbt mode is contained. the following function can be used to achieve the motor control. ? pwm signal output function ? dc chopper waveform output function ? dead time function ? input capture function ? ad c start function ? dtif ( m otor emergen cy stop) interrupt function real - time c lock (rtc) the real - time c lock count s y ear/ m onth/ d ay/ h our/ m inute/ s econd/ d ay of the week from year 01 to year 99. ? the rtc can generate an interrupt at a specific time (y ear/ m onth/ d ay/ h our/ m inute/ s econd/ d ay of the week ) and can also generate an interrupt in a specific year, in a specific month, on a specific day, at a specific hour or at a specific minute. ? it has a timer interrupt function generating an interrupt upon a specific time or at specific intervals. ? it can keep counting while rewriting the time. ? it can count leap years automatically .
document number: 002 - 05091 rev.*a page 3 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a watch counter the watch c ounter wake s up the microcontroller from the low power consumption mode. the clock source can be selected from the main clock, the sub clock, the built - in high - speed cr clock or the built - in low - speed cr clock. interval timer: up to 64 s (s ub c lock : 32.768 khz ) external interrupt controller unit ? up to 8 external interrupt input pins ? non - maskable interrupt (nmi) input pin: 1 watchdog t imer (2 channels) the watchdog timer generate s an interrupt or a reset when the counter reaches a time - out value. this series consists of two different watchdogs, "h ardware " watchdog and "s oftware " watchdog. the "h ardware " watchdog timer is clocked by the built - in low - speed cr oscillator. therefore , the "h ardware" watchdog is active in any low - power consumption modes except rtc mode and stop mode. clock and reset ? clocks a clock can be selected from five clock sources ( two external oscillator s, two built - in cr oscil lator , and m ain pll). ? main clock : 4 mhz to 4 0 mhz ? sub clock : 32.768 khz ? built - in high - speed cr clock : 4 mhz ? built - in low - speed cr clock : 100 khz ? main pll clock ? resets ? reset request from the initx pin ? power on reset ? software reset ? watchdog timer reset ? low - voltage detection reset ? clock supervisor reset clock supervisor (csv) the clock supervisor monitors the failure of external clocks with a clock generated by a built - in cr oscillator. ? if an external clock failure (clock stop) is detected, a reset is asserted. ? if an external frequency anomaly is detected, an interrupt or a reset is asserted. low - v oltage detector (lvd) this s eries monitors the voltage on the vcc pin with a 2 - stage mechanism. when the voltage falls below a designated voltage, the low - voltage detector generates an interrupt or a reset. ? lvd1: error reporting via an interrupt ? lvd2: auto - reset operation low power c onsumption m ode this series has f our low power consumption modes. ? sleep ? timer ? rtc ? stop peripheral clock gating the system can reduce the current consumption of the total system with gating the operation clocks of peripheral functions not used. debug ? serial wire debug port (sw - dp) ? micro trace buffer (mtb) unique id a 41 - bit unique value of the device has been set. power supply wide voltage range : vcc = 2.7 v to 5.5 v
document number: 002 - 05091 rev.*a page 4 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a contents 1. product lineup ................................ ................................ ................................ ................................ ................................ .. 5 2. packages ................................ ................................ ................................ ................................ ................................ ........... 6 3. pin assignment ................................ ................................ ................................ ................................ ................................ . 7 4. pin descripti ons ................................ ................................ ................................ ................................ .............................. 12 5. i/o circuit type ................................ ................................ ................................ ................................ ............................... 23 6. handling precautions ................................ ................................ ................................ ................................ ..................... 28 6.1 prec autions for product design ................................ ................................ ................................ ................................ ... 28 6.2 precautions for package mounting ................................ ................................ ................................ .............................. 29 6.3 precautions for use environment ................................ ................................ ................................ ................................ 31 7. handling devices ................................ ................................ ................................ ................................ ............................ 32 8. block diagram ................................ ................................ ................................ ................................ ................................ . 35 9. memory size ................................ ................................ ................................ ................................ ................................ .... 36 10. memory map ................................ ................................ ................................ ................................ ................................ .... 36 11. pin status in each cpu state ................................ ................................ ................................ ................................ ........ 39 12. electrical characteristics ................................ ................................ ................................ ................................ ............... 43 12 .1 absolute maximum ratings ................................ ................................ ................................ ................................ ......... 43 12.2 recommended operating conditions ................................ ................................ ................................ ......................... 44 12.3 dc characteristics ................................ ................................ ................................ ................................ ...................... 45 12.3.1 c urrent rating ................................ ................................ ................................ ................................ .............................. 45 12.3.2 pin characteristics ................................ ................................ ................................ ................................ ....................... 48 12.4 ac characteristics ................................ ................................ ................................ ................................ ....................... 49 12.4.1 m ain clock input characteristics ................................ ................................ ................................ ................................ .. 49 12.4.2 sub clock input characteristics ................................ ................................ ................................ ................................ ... 50 12.4.3 built - in cr oscillation characteristics ................................ ................................ ................................ .......................... 51 12.4.4 operating conditions of main pll (in the case of using the main clock as the input clock of the pll) ....................... 52 12.4.5 operating conditions of main pll (in the case of using the built - in high - speed cr clock as the input clock of the main pll) ................................ ................................ ................................ .............................. 52 12.4.6 reset input characteristics ................................ ................................ ................................ ................................ .......... 53 12.4.7 power - on reset timing ................................ ................................ ................................ ................................ ................ 53 12.4.8 base timer input timing ................................ ................................ ................................ ................................ .............. 54 12.4.9 csio timing ................................ ................................ ................................ ................................ ................................ . 55 12.4.10 external input timing ................................ ................................ ................................ ................................ ................ 71 12.4.11 qprc timing ................................ ................................ ................................ ................................ ........................... 72 12.4.12 i 2 c timing ................................ ................................ ................................ ................................ ................................ . 74 12.4.13 sw - dp timing ................................ ................................ ................................ ................................ .......................... 75 12.5 12 - bit a/d converter ................................ ................................ ................................ ................................ .................... 76 12.6 low - voltage detection characteristics ................................ ................................ ................................ ........................ 79 12.6.1 low - voltage detection reset ................................ ................................ ................................ ................................ ....... 79 12.6.2 low - voltage detection interrupt ................................ ................................ ................................ ................................ ... 80 12.7 flash memory write/erase characteristics ................................ ................................ ................................ ................. 81 12.8 return time from low - power consumption mode ................................ ................................ ................................ ...... 82 12.8.1 return factor: interrupt ................................ ................................ ................................ ................................ ................ 82 12.8.2 return factor: reset ................................ ................................ ................................ ................................ .................... 84 13. ordering information ................................ ................................ ................................ ................................ ...................... 86 14. package dimensions ................................ ................................ ................................ ................................ ...................... 87 15. major changes ................................ ................................ ................................ ................................ ................................ 92
document number: 002 - 05091 rev.*a page 5 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 1. p roduct l ineup memory s ize product name s6e1a11b0a s6e1a11c0a s6e1a12b0a s6e1a12c0a on - chip flash memory 56 kbyte 88 kbyte on - chip s ram 6 kbyte 6 kbyte function product name s6e1a11b0a s6e1a1 2b 0a s6e1a1 1c 0a s6e1a12c0a pin count 32 48 /52 cpu cortex - m0+ freq uency 40 mhz power supply voltage range 2.7 v to 5.5 v dmac 2 ch . multi - function serial interface (uart/csio/i 2 c) 3 ch. (max) ch.0/ch.1 /ch.3 : fifo base timer (pwc/reload timer/pwm/ppg) 4 ch . (max) m ulti - functio n timer a/d start compare 6 ch. 1 unit input capture 4 ch. free - run timer 3 ch. output compare 6 ch. waveform generator 3 ch. ppg 3 ch. qprc 1 ch . dual timer 1 unit real - time clock 1 unit watch counter 1 unit watchdog timer 1 ch. (sw) + 1 ch. (hw) external interrupt 8 pins (max) + nmi 1 i/o port 23 pins (max) 37 pins (max) 12 - bit a/d converter 5 ch . ( 1 unit) 8 ch . ( 1 unit) csv (clock super v isor) yes lvd (low - v oltage detect ion ) 2 ch. built - in cr high - speed 4 mhz low - speed 100 khz debug function sw - dp unique id yes note : ? all signals of the peripheral function in each product cannot be allocated by limiting the pins of package. it is necessary to use the port relocate function of the i/o port according to your function use. see " 14. electrical characteristics 14. 4 ac characteristics 14.4.3 built - in cr o scillation characteristics" for accuracy of built - in cr.
document number: 002 - 05091 rev.*a page 6 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 2. p ackages product name package s6e1a11b0a s6e1a12b0a s6e1a11c0a s6e1a12c0a lqfp : fpt - 32p - m30 ( 0.80 mm pitch) ? - qfn : lcc - 32p - m 73 (0.50 mm pitch) ? - lqfp : fpt - 48p - m49 (0.50 mm pitch) - ? qfn : lcc - 48p - m 74 (0.50 mm pitch) - ? lqfp : fpt - 52p - m02 ( 0.65 mm pitch) - ? ? : supported note: ? see " 14 . package dimensions " for detailed information on each package.
document number: 002 - 05091 rev.*a page 7 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 3. p in a ssignment fpt - 32 p - m3 0 (top view ) note : ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. 32 31 30 29 28 27 26 25 p3a/rto00_0/tioa0_1/ain0_3/subout_2/rtcco_2/int03_0/sck0_2 1 24 p22/an07/sot0_0/tiob2_0/ic03_1/zin0_1/int05_1 p3b/rto01_0/tioa1_1/bin0_3/sot0_2/int04_0/scs31_2 2 23 p23/an06/sck0_0/tioa2_0/ic02_1/ain0_1/int04_1 p3c/rto02_0/tioa2_1/zin0_3/sin0_2/int05_0/scs30_2 3 22 avss p3d/rto03_0/tioa3_1/int06_0/ain0_0/sck3_2 4 21 avcc p3e/rto04_0/tioa0_0/bin0_0/sot3_2/int15_0 5 20 p13/an03/sck1_1/subout_1/ic01_2/rtcco_1/int00_1 p3f/rto05_0/tioa1_0/zin0_0/sin3_2 6 19 p12/an02/sot1_1/ic00_2/int01_1 vss 7 18 p11/an01/sin1_1/int02_1/frck0_2/ic02_0 c 8 17 vss 9 10 11 12 13 14 15 16 vss p60/sin3_0/tioa2_2/int15_1/ic00_0/igtrg0_0/scs10_2 p61/sot3_0/tiob2_2/dtti0x_2/scs11_2 p0f/nmix/subout_0/crout_1/rtcco_0 p04/sck3_0/int03_2/tiob0_1/igtrg0_1 p03/swdio p01/swclk p21/sin0_0/int06_1/tiob1_1/ic01_1/bin0_1/frck0_0 vcc p46/x0a p47/x1a initx pe0/adtg_1/dtti0x_1/int02_2 md0 pe2/x0 pe3/x1 lqfp - 32
document number: 002 - 05091 rev.*a page 8 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a lcc - 32 p - m 73 (top view) note : ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. 32 31 30 29 28 27 26 25 p3a/rto00_0/tioa0_1/ain0_3/subout_2/rtcco_2/int03_0/sck0_2 1 24 p22/an07/sot0_0/tiob2_0/ic03_1/zin0_1/int05_1 p3b/rto01_0/tioa1_1/bin0_3/sot0_2/int04_0/scs31_2 2 23 p23/an06/sck0_0/tioa2_0/ic02_1/ain0_1/int04_1 p3c/rto02_0/tioa2_1/zin0_3/sin0_2/int05_0/scs30_2 3 22 avss p3d/rto03_0/tioa3_1/int06_0/ain0_0/sck3_2 4 21 avcc p3e/rto04_0/tioa0_0/bin0_0/sot3_2/int15_0 5 20 p13/an03/sck1_1/subout_1/ic01_2/rtcco_1/int00_1 p3f/rto05_0/tioa1_0/zin0_0/sin3_2 6 19 p12/an02/sot1_1/ic00_2/int01_1 vss 7 18 p11/an01/sin1_1/int02_1/frck0_2/ic02_0 c 8 17 vss 9 10 11 12 13 14 15 16 pe0/adtg_1/dtti0x_1/int02_2 p01/swclk p21/sin0_0/int06_1/tiob1_1/ic01_1/bin0_1/frck0_0 vcc p46/x0a p47/x1a initx md0 pe2/x0 pe3/x1 vss p60/sin3_0/tioa2_2/int15_1/ic00_0/igtrg0_0/scs10_2 p61/sot3_0/tiob2_2/dtti0x_2/scs11_2 p0f/nmix/subout_0/crout_1/rtcco_0 p04/sck3_0/int03_2/tiob0_1/igtrg0_1 p03/swdio qfn - 32
document number: 002 - 05091 rev.*a page 9 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a fpt - 48 p - m 49 (top view) note : ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple p ins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. 48 47 46 45 44 43 42 41 40 39 38 37 vcc 1 36 p21/sin0_0/int06_1/tiob1_1/ic01_1/bin0_1/frck0_0 p50/int00_0/ain0_2/sin3_1/ic01_0 2 35 p22/an07/sot0_0/tiob2_0/ic03_1/zin0_1/int05_1 p51/int01_0/bin0_2/sot3_1 3 34 p23/an06/sck0_0/tioa2_0/ic02_1/ain0_1/int04_1 p52/int02_0/zin0_2/sck3_1 4 33 avss p39/dtti0x_0/adtg_2 5 32 avrh p3a/rto00_0/tioa0_1/ain0_3/subout_2/rtcco_2/int03_0/sck0_2 6 31 avcc p3b/rto01_0/tioa1_1/bin0_3/sot0_2/int04_0/scs31_2 7 30 p15/an05/sot0_1/scs11_1/ic03_2/int15_2 p3c/rto02_0/tioa2_1/zin0_3/sin0_2/int05_0/scs30_2 8 29 p14/an04/sin0_1/scs10_1/int03_1/ic02_2 p3d/rto03_0/tioa3_1/int06_0/ain0_0/sck3_2 9 28 p13/an03/sck1_1/subout_1/ic01_2/rtcco_1/int00_1 p3e/rto04_0/tioa0_0/bin0_0/sot3_2/int15_0 10 27 p12/an02/sot1_1/ic00_2/int01_1 p3f/rto05_0/tioa1_0/zin0_0/sin3_2 11 26 p11/an01/sin1_1/int02_1/frck0_2/ic02_0 vss 12 25 p10/an00 13 14 15 16 17 18 19 20 21 22 23 24 p60/sin3_0/tioa2_2/int15_1/ic00_0/igtrg0_0/scs10_2 vss p82/sin1_2 p81/sot1_2 p80/sck1_2/frck0_1 p61/sot3_0/tiob2_2/dtti0x_2/scs11_2 p0f/nmix/subout_0/crout_1/rtcco_0 p04/sck3_0/int03_2/tiob0_1/igtrg0_1 p03/swdio p02 p01/swclk p00 c vcc p46/x0a p47/x1a initx p49/tiob0_0 p4a/tiob1_0 pe0/adtg_1/dtti0x_1/int02_2 md0 pe2/x0 pe3/x1 vss lqfp - 48
document number: 002 - 05091 rev.*a page 10 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a lcc - 48 p - m 74 (top view) note : ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. 48 47 46 45 44 43 42 41 40 39 38 37 vcc 1 36 p21/sin0_0/int06_1/tiob1_1/ic01_1/bin0_1/frck0_0 p50/int00_0/ain0_2/sin3_1/ic01_0 2 35 p22/an07/sot0_0/tiob2_0/ic03_1/zin0_1/int05_1 p51/int01_0/bin0_2/sot3_1 3 34 p23/an06/sck0_0/tioa2_0/ic02_1/ain0_1/int04_1 p52/int02_0/zin0_2/sck3_1 4 33 avss p39/dtti0x_0/adtg_2 5 32 avrh p3a/rto00_0/tioa0_1/ain0_3/subout_2/rtcco_2/int03_0/sck0_2 6 31 avcc p3b/rto01_0/tioa1_1/bin0_3/sot0_2/int04_0/scs31_2 7 30 p15/an05/sot0_1/scs11_1/ic03_2/int15_2 p3c/rto02_0/tioa2_1/zin0_3/sin0_2/int05_0/scs30_2 8 29 p14/an04/sin0_1/scs10_1/int03_1/ic02_2 p3d/rto03_0/tioa3_1/int06_0/ain0_0/sck3_2 9 28 p13/an03/sck1_1/subout_1/ic01_2/rtcco_1/int00_1 p3e/rto04_0/tioa0_0/bin0_0/sot3_2/int15_0 10 27 p12/an02/sot1_1/ic00_2/int01_1 p3f/rto05_0/tioa1_0/zin0_0/sin3_2 11 26 p11/an01/sin1_1/int02_1/frck0_2/ic02_0 vss 12 25 p10/an00 13 14 15 16 17 18 19 20 21 22 23 24 p4a/tiob1_0 pe0/adtg_1/dtti0x_1/int02_2 md0 pe2/x0 pe3/x1 vss c vcc p46/x0a p47/x1a initx p49/tiob0_0 p0f/nmix/subout_0/crout_1/rtcco_0 p04/sck3_0/int03_2/tiob0_1/igtrg0_1 p03/swdio p02 p01/swclk p00 vss p82/sin1_2 p81/sot1_2 p80/sck1_2/frck0_1 p60/sin3_0/tioa2_2/int15_1/ic00_0/igtrg0_0/scs10_2 p61/sot3_0/tiob2_2/dtti0x_2/scs11_2 qfn - 48
document number: 002 - 05091 rev.*a page 11 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a fpt - 52 p - m 02 (top view) note: ? the number after the underscore ("_") in a pin name such as xxx_1 and xxx_2 indic ates the relocated port number. the channel on such pin has multiple functions, each of which has its own pin name. use the e xtended p ort f unction r egister (epfr) to select the pin to be used . 52 51 50 49 48 47 46 45 44 43 42 41 40 vcc 1 39 p21/sin0_0/int06_1/tiob1_1/ic01_1/bin0_1/frck0_0 p50/int00_0/ain0_2/sin3_1/ic01_0 2 38 p22/an07/sot0_0/tiob2_0/ic03_1/zin0_1/int05_1 p51/int01_0/bin0_2/sot3_1 3 37 p23/an06/sck0_0/tioa2_0/ic02_1/ain0_1/int04_1 p52/int02_0/zin0_2/sck3_1 4 36 nc nc 5 35 avss p39/dtti0x_0/adtg_2 6 34 avrh p3a/rto00_0/tioa0_1/ain0_3/subout_2/rtcco_2/int03_0/sck0_2 7 33 avcc p3b/rto01_0/tioa1_1/bin0_3/sot0_2/int04_0/scs31_2 8 32 p15/an05/sot0_1/scs11_1/ic03_2/int15_2 p3c/rto02_0/tioa2_1/zin0_3/sin0_2/int05_0/scs30_2 9 31 p14/an04/sin0_1/scs10_1/int03_1/ic02_2 p3d/rto03_0/tioa3_1/int06_0/ain0_0/sck3_2 10 30 p13/an03/sck1_1/subout_1/ic01_2/rtcco_1/int00_1 p3e/rto04_0/tioa0_0/bin0_0/sot3_2/int15_0 11 29 p12/an02/sot1_1/ic00_2/int01_1 p3f/rto05_0/tioa1_0/zin0_0/sin3_2 12 28 p11/an01/sin1_1/int02_1/frck0_2/ic02_0 vss 13 27 p10/an00 14 15 16 17 18 19 20 21 22 23 24 25 26 md0 pe2/x0 pe3/x1 vss p47/x1a initx p49/tiob0_0 p4a/tiob1_0 nc pe0/adtg_1/dtti0x_1/int02_2 c vcc p46/x0a nc p0f/nmix/subout_0/crout_1/rtcco_0 p04/sck3_0/int03_2/tiob0_1/igtrg0_1 p03/swdio p02 p01/swclk p00 vss p82/sin1_2 p81/sot1_2 p80/sck1_2/frck0_1 p60/sin3_0/tioa2_2/int15_1/ic00_0/igtrg0_0/scs10_2 p61/sot3_0/tiob2_2/dtti0x_2/scs11_2 lqfp - 52
document number: 002 - 05091 rev.*a page 12 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 4. p in d escriptions l ist of p in f unctions the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function registe r (epfr) to select the pin. pin no. pin name i/o circuit type pin state type l qfp - 52 lqfp - 48 qfn - 48 l qfp - 32 qfn - 32 1 1 - v cc - 2 2 - p50 i* j int00_0 ain0_2 sin3_1 ic01_0 3 3 - p51 i* j int01_0 bin0_2 sot3_1 4 4 - p52 i* j int02_0 zin0_2 sck3_1 6 5 - p39 e i dtti0x_0 adtg_2 7 6 1 p3a f j rto00_0 tioa0_1 ain0_3 subout_2 rtcco_2 int03_0 sck0_2 8 7 2 p3b f j rto01_0 tioa1_1 bin0_3 sot0_2 int04_0 scs31_2
document number: 002 - 05091 rev.*a page 13 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a pin no. pin name i/o circuit type pin state type l qfp - 52 lqfp - 48 qfn - 48 l qfp - 32 qfn - 32 9 8 3 p3c f j rto02_0 tioa2_1 zin0_3 sin0_2 int05_0 scs30_2 10 9 4 p3d f j rto03_0 tioa3_1 int06_0 ain0_0 sck3_2 1 1 10 5 p3e f j rto04_0 tioa0_0 bin0_0 sot3_2 int15_0 1 2 11 6 p3f f i rto05_0 tioa1_0 zin0_0 sin3_2 1 3 12 7 vss - 1 4 13 8 c - 1 5 14 9 vcc - 1 6 15 10 p46 d e x0a 1 7 16 11 p47 d f x1a 1 8 17 12 initx b c 1 9 18 - p49 e i tiob0_0 20 19 - p4a e i tiob1_0
document number: 002 - 05091 rev.*a page 14 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a pin no. pin name i/o circuit type pin state type l qfp - 52 lqfp - 48 qfn - 48 l qfp - 32 qfn - 32 2 2 20 13 pe0 c j adtg_1 dtti0x_1 int02_2 23 21 14 md0 j d 2 4 22 15 pe2 a a x0 2 5 23 16 pe3 a b x1 2 6 24 17 vss - 2 7 25 - p10 g k an00 2 8 26 18 p11 h* l an01 sin1_1 int02_1 frck0_2 ic02_0 2 9 27 19 p12 h* l an02 sot1_1 ic00_2 int01_1 30 28 20 p13 h* l an03 sck1_1 subout_1 ic01_2 rtcco_1 int00_1 31 29 - p14 h* l an04 sin0_1 scs10_1 int03_1 ic02_2
document number: 002 - 05091 rev.*a page 15 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a pin no. pin name i/o circuit type pin state type l qfp - 52 lqfp - 48 qfn - 48 l qfp - 32 qfn - 32 3 2 30 - p15 h* l an05 sot0_1 scs11_1 ic03_2 int15_2 3 3 31 21 avcc - 3 4 32 - avrh - 3 5 33 22 avss - 3 7 34 23 p23 g l an06 sck0_0 tioa2_0 ic02_1 ain0_1 int04_1 3 8 35 24 p22 g l an07 sot0_0 tiob2_0 ic03_1 zin0_1 int05_1 3 9 36 25 p21 e j sin0_0 int06_1 tiob1_1 ic01_1 bin0_1 frck0_0 41 37 - p00 e i 42 38 26 p01 e h swclk 43 39 - p02 e i 4 4 40 27 p03 e h swdio
document number: 002 - 05091 rev.*a page 16 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a pin no. pin name i/o circuit type pin state type l qfp - 52 lqfp - 48 qfn - 48 l qfp - 32 qfn - 32 4 5 41 28 p04 i* j sck3_0 int03_2 tiob0_1 igtrg0_1 4 6 42 29 p0f e g nmix subout_0 crout_1 rtcco_0 4 7 43 30 p61 i* i sot3_0 tiob2_2 dtti0x_2 scs11_2 4 8 44 31 p60 i* j sin3_0 tioa2_2 int15_1 ic00_0 igtrg0_0 scs10_2 4 9 45 - p80 k i sck1_2 frck0_1 50 46 - p81 k i sot1_2 51 47 - p82 k i sin1_2 52 48 32 vss - 5,21,36,40 - - nc - * :5v tolerant i/o
document number: 002 - 05091 rev.*a page 17 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a list of pin functions the number after the underscore ("_") in a pin name such as xxx_1 and xxx_2 indic ates the relocated port number. the channel on such pin has multiple functions, each of which has its own pin name. use the e xtended p ort f unction r egister (epfr) to select the pin to be used . pin function pin name function description pin n o . lqfp - 52 lqfp - 48 qfn - 48 lqfp - 32 qfn - 32 adc adtg_ 1 a/d converter external trigger input pin 22 20 13 adtg_ 2 6 5 - an00 a/d converter analog input pin. anxx describes adc ch.xx. 27 25 - an01 28 26 18 an02 29 27 19 an03 30 28 20 an04 31 29 - an05 32 30 - an06 37 34 23 an07 38 35 24 base timer 0 tioa0_0 base timer ch.0 tioa pin 11 10 5 tioa0_1 7 6 1 tiob0_0 base timer ch.0 tiob pin 19 18 - tiob0_1 45 41 28 base timer 1 tioa1_0 base timer ch.1 tioa pin 12 11 6 tioa1_1 8 7 2 tiob1_0 base timer ch.1 tiob pin 20 19 - tiob1_1 39 36 25 base timer 2 tioa2_0 base timer ch.2 tioa pin 37 34 23 tioa2_1 9 8 3 tioa2_2 48 44 31 tiob2_0 base timer ch.2 tiob pin 38 35 24 tiob2_2 47 43 30 base timer 3 tioa3_1 base timer ch.3 tioa pin 10 9 4 debugger swclk serial wire debug interface clock input pin 42 38 26 swdio serial wire debug interface data input / output pin 44 40 27
document number: 002 - 05091 rev.*a page 18 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a pin function pin name function description pin n o . lqfp - 52 lqfp - 48 qfn - 48 lqfp - 32 qfn - 32 external interrupt int00_0 external interrupt request 00 input pin 2 2 - int00_1 30 28 20 int01_0 external interrupt request 01 input pin 3 3 - int01_1 29 27 19 int02_0 external interrupt request 02 input pin 4 4 - int02_1 28 26 18 int02_ 2 22 20 13 int03_0 external interrupt request 03 input pin 7 6 1 int03_1 31 29 - int03_2 45 41 28 int04_0 external interrupt request 04 input pin 8 7 2 int04_1 37 34 23 int05_0 external interrupt request 05 input pin 9 8 3 int05_1 38 35 24 int06_0 external interrupt request 06 input pin 10 9 4 int06_1 39 36 25 int15_ 0 external interrupt request 15 input pin 11 10 5 int15_1 48 44 31 int15_ 2 32 30 - nmix non - maskable interrupt input pin 46 42 29
document number: 002 - 05091 rev.*a page 19 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a pin function pin name function description pin n o . lqfp - 52 lqfp - 48 qfn - 48 lqfp - 32 qfn - 32 gpio p00 general - purpose i/o port 0 41 37 - p01 42 38 26 p02 43 39 - p03 44 40 27 p04 45 41 28 p0f 46 42 29 p10 general - purpose i/o port 1 27 25 - p11 28 26 18 p12 29 27 19 p13 30 28 20 p14 31 29 - p15 32 30 - p21 general - purpose i/o port 2 39 36 25 p22 38 35 24 p23 37 34 23 p39 general - purpose i/o port 3 6 5 - p3a 7 6 1 p3b 8 7 2 p3c 9 8 3 p3d 10 9 4 p3e 11 10 5 p3f 12 11 6 gpio p46 general - purpose i/o port 4 16 15 10 p47 17 16 11 p49 19 18 - p4a 20 19 - p50 general - purpose i/o port 5 2 2 - p51 3 3 - p52 4 4 - p60 general - purpose i/o port 6 48 44 31 p61 47 43 30 p80 general - purpose i/o port 8 49 45 - p81 50 46 - p82 51 47 - pe0 * general - purpose i/o port e 22 20 13 pe2 24 22 15 pe3 25 23 16
document number: 002 - 05091 rev.*a page 20 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a pin function pin name function description pin n o . lqfp - 52 lqfp - 48 qfn - 48 lqfp - 32 qfn - 32 multi - functio n serial 0 sin0_0 multi - function serial interface ch.0 input pin 39 36 25 sin0_1 31 29 - sin0_ 2 9 8 3 sot0_0 (sda0_0) multi - function serial interface ch.0 output pin. this pin operates as sot0 when used as a uart/csio/lin pin (operation mode 0 to 3) and as sda0 when used as an i 2 c pin (operation mode 4). 38 35 24 sot0_1 (sda0_1) 32 30 - sot0_ 2 (sda0_ 2 ) 8 7 2 sck0_0 (scl0_0) multi - function serial interface ch.0 clock i/o pin. this pin operates as sck0 when used as a csio pin (operation mode 2) and as scl0 when u sed as an i 2 c pin (operation mode 4). 37 34 23 sck0_ 2 (scl0_ 2 ) 7 6 1 multi - functio n serial 1 sin1_1 multi - function serial interface ch.1 input pin 28 26 18 sin1_ 2 51 47 - sot1_1 (sda1_1) multi - function serial interface ch. 1 output pin. this pin operates as sot 1 when used as a uart/csio/lin pin (operation mode 0 to 3) and as sda 1 when used as an i 2 c pin (operation mode 4). 29 27 19 sot1_ 2 (sda1_ 2 ) 50 46 - sck1_1 (scl1_1) multi - function serial interface ch.1 clock i/o pin . this pin operates as sck1 when used as a csio pin (operation mode 2) and as scl1 when used as an i 2 c pin (operation mode 4). 30 28 20 sck1_ 2 (scl1_ 2 ) 49 45 - scs10_1 multi - function serial interface ch. 1 serial chip select 0 output/input pin . 31 29 - scs1 0 _ 2 48 44 31 scs1 1 _ 1 multi - function serial interface ch. 1 serial chip select 1 output pin . 32 30 - scs1 1 _ 2 47 43 30 multi - function serial 3 sin3_0 multi - functi on serial interface ch.3 input pin 48 44 31 sin3_1 2 2 - sin3_ 2 12 11 6 sot3_0 (sda3_ 0 ) multi - function serial interface ch.3 output pin. this pin operates as sot3 when used as a uart/csio/lin pin (operation mode 0 to 3) and as sda3 when used as an i 2 c pin (operation mode 4). 47 43 30 sot3_ 1 (sda3_1) 3 3 - sot3_ 2 (sda3_ 2 ) 11 10 5 sck3_ 0 (scl3_ 0 ) multi - function serial interface ch.3 clock i/o pin. this pin operates as sck3 when used as a csio (operation mode 2) and as scl3 when used as an i 2 c pin (operation mode 4). 45 41 28 sck3_ 1 (scl3_ 1 ) 4 4 - sck3_ 2 (scl3_ 2 ) 10 9 4 scs30_2 multi - function serial interface ch. 3 serial chip select 0 input/output pin . 9 8 3 scs3 1 _2 multi - function serial interface ch. 3 serial chip select 1 output pin . 8 7 2
document number: 002 - 05091 rev.*a page 21 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a pin function pin name function description pin n o . lqfp - 52 lqfp - 48 qfn - 48 lqfp - 32 qfn - 32 multi - functio n timer 0 dtti0x_ 0 input signal of waveform generator control ling rto00 to rto05 outputs of multi - function t imer 0. 6 5 - dtti0x_ 1 22 20 13 dtti0x_ 2 47 43 30 frck0_0 16 - bit free - run timer ch.0 external clock input pin . 39 36 25 frck0_ 1 49 45 - frck0_2 28 26 18 ic00_0 16 - bit input capture input pin of multi - function timer 0. icxx describes channel number. 48 44 31 ic00_2 29 27 19 ic01_0 2 2 - ic01_ 1 39 36 25 ic01_2 30 28 20 ic02_0 28 26 18 ic02_ 1 37 34 23 ic02_2 31 29 - ic03_ 1 38 35 24 ic03_2 32 30 - rto00_0 (ppg00_0) waveform generator output pin of multi - function timer 0. this pin operates as ppg00 when it is used in ppg0 output mode. 7 6 1 rto01_0 (ppg0 0 _0) waveform generator output pin of multi - function timer 0. this pin operates as ppg00 when it is used in ppg0 output mode. 8 7 2 rto02_0 (ppg02_0) waveform generator output pin of multi - function timer 0. this pin operates as ppg02 when it is used in ppg0 output mode. 9 8 3 rto03_0 (ppg02_0) waveform generator output pin of multi - function timer 0. this pin operates as ppg02 when it is used in ppg0 output mode. 10 9 4 rto04_0 (ppg04_0) waveform generator output pin of multi - function timer 0. this pin operates as ppg04 when it is used in ppg0 output mode. 11 10 5 rto05_0 (ppg04_0) waveform generator output pin of multi - function timer 0. this pin operates as ppg04 when it is used in ppg0 output mode. 12 11 6 igtrg0_ 0 ppg igbt mode external trigger input pin 48 44 31 igtrg0_1 45 41 28
document number: 002 - 05091 rev.*a page 22 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a pin function pin name function description pin n o . lqfp - 52 lqfp - 48 qfn - 48 lqfp - 32 qfn - 32 quadrature position/ revolution counter ain 0 _ 0 qprc ch. 0 ain input pin 10 9 4 ain 0 _1 37 34 23 ain 0 _2 2 2 - ain 0 _ 3 7 6 1 bin 0 _0 qprc ch. 0 bin input pin 11 10 5 bin 0 _1 39 36 25 bin 0 _2 3 3 - bin 0 _ 3 8 7 2 zin 0 _0 qprc ch. 0 zin input pin 12 11 6 zin 0 _1 38 35 24 zin 0 _2 4 4 - zin 0 _ 3 9 8 3 real - time clock rtcco_0 0.5 - seconds pulse output pin of real - time clock 46 42 29 rtcco_1 30 28 20 rtcco_2 7 6 1 subout_0 sub clock output pin 46 42 29 subout_1 30 28 20 subout_2 7 6 1 reset initx external reset input pin. a reset is valid when initx="l". 18 17 12 mode md0 mode 0 pin. during normal operation, input md0="l". during serial programming to flash memory, input md0="h " . 23 21 14 power vcc p ower supply p in 1 1 - vcc p ower supply p in 15 14 9 gnd vss gnd p in 13 12 7 vss gnd p in 26 24 17 vss gnd p in 52 48 32 clock x0 main clock (oscillation) input pin 24 22 15 x0a sub clock (oscillation) input pin 16 15 10 x1 main clock (oscillation) i/o pin 25 23 16 x1a sub clock (oscillation) i/o pin 17 16 11 crout_1 built - in high - speed c r oscillation clock output port 46 42 29 analog power avcc a/d converter analog power supply pin 33 31 21 avrh a/d converter analog reference voltage input pin 34 32 - analog gnd av ss a/d converter analog reference voltage input pin 35 33 22 c pin c power supply stabilization capacitance pin 14 13 8 * : pe0 is an open drain pin, cannot output high.
document number: 002 - 05091 rev.*a page 23 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 5. i/o c ircuit t ype type circuit remarks a it is possible to select the main oscillation / gpio function when the main oscillation is selected. ? oscillation feedback resistor : approximately 1m ? with s tandby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? wit h pull - up resistor control ? with standby mode control ? pul l - up resistor : approximately 50 k ? i oh = - 4ma, i ol = 4ma b ? cmos level hysteresis input ? pul l - up resistor : approximately 50 k digital output digital output pull - up resistor control digital input standby mode c ontrol clock input standby mode c ontrol digital input standby mode c ontrol digital output digital output pull - up resistor control pull - up resistor digital in put p-ch p-ch n-ch r r p-ch p-ch n-ch x0 x1
document number: 002 - 05091 rev.*a page 24 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a type circuit remarks c ? open drain output ? cmos level hysteresis input d it is possible to select the sub oscillation / gpio function when the sub oscillation is selected. ? oscillation feedback resistor : approximately 5m ? with s tandby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pul l - up resistor : approximately 50 k ? i oh = - 4ma, i ol = 4ma digital input digital out put digital output digital output pull - up resistor control digital input standby mode c ontrol clock input standby mode c ontrol digital input standby mode c ontrol digital output digital output pull - up resistor control n-ch p-ch p-ch n-ch r r p-ch p-ch n-ch x0 a x1 a
document number: 002 - 05091 rev.*a page 25 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a type circuit remarks e ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pul l - up resistor : approximately 50 k ? i oh = - 4ma, i ol = 4ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off f ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pul l - up resistor : approximately 50 k ? i oh = - 12 ma, i ol = 12 ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off digital output digital output pull - up resistor control digital input standby mode c ontrol digital output digital output pull - up resistor control digital input standby mode c ontrol p-ch p-ch n-ch r
document number: 002 - 05091 rev.*a page 26 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a type circuit remarks g ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? with pull - up resistor control ? with standby mode control ? pul l - up resistor : approximately 50 k ? i oh = - 4ma, i ol = 4ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off h ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? 5v tolerant ? with pull - up resistor control ? with standby mode control ? pul l - up resistor : approximately 50 k ? i oh = - 4ma, i ol = 4ma ? available to control of pzr registers. ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off digital output digital output pull - up resistor control digital input standby mode c ontrol analog input input control digital output digital output pull - up resistor control digital input standby mode c ontrol analog input input control p-ch p-ch n-ch r
document number: 002 - 05091 rev.*a page 27 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a type circuit remarks i ? cmos level output ? cmos level hysteresis input ? 5v tolerant ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50k ? i oh = - 4ma, i ol = 4ma ? available to control pzr registers ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off j cmos level hysteresis input k ? cmos level output ? cmos level hysteresis input ? with standby mode control ? i oh = - 4ma, i ol = 4ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off mode input digital output digital output pull - up resistor control digital input standby mode c ontrol digital output digital output digital input standby mode control p-ch p-ch n-ch r p-ch n-ch r
document number: 002 - 05091 rev.*a page 28 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 6. h andling p recautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the co nditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions th at must be observed to minimize the chance of failure and to obtain higher reliability from your cypress semiconductor devices. 6.1 precautions for product design this section describes precautions when designing electronic equipment using semiconductor device s. absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recomme nded operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users consider ing application outside the listed conditions are advised to contact their sales representative beforehand. processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the dev ice, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. 2. protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows . such condit ions if present for extended periods of time can damage the device. therefore, avoid this type of connection. 3. handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. code: ds00 - 00004 - 2ea
document number: 002 - 05091 rev.*a page 29 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high voltag es, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch - up. caution: the occurrence of latc h - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: 1. be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. 2. be sure that abnormal current flows do not occur during the power - on sequence. observance of safety regulations and standards most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. fail - safe design any semiconductor devices have inherently a c ertain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnorma l operating conditions. precautions related to usage of devices cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, per sonal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may direct ly affect human lives or cause physical injury or property damage, or where extremely high level s of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. 6.2 precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during solderin g, you should only mount under cypress 's recommended conditions. for detailed information about mount conditions, contact your sales representative. lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct so ldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. in this case, t he soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic lead s be verified before mounting. surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connec t ions caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount pa ckages in accordance with cypress ranking of recommended conditions.
document number: 002 - 05091 rev.*a page 30 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a lead - free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be reduced under some conditions of use. storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorpt ion of moistur e. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: 1. avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature changes are slight. 2. use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 c and 30 c . when you o pen dry package that recommends humidity 40% to 70% relative humidity. 3. when necessary, cypress packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum lamin ate bags for storage. 4. avoid storing packages where they are exposed to corrosive gases or high levels of dust. baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the cypress recommended conditions for baking. condition: 125 c /24 h static electricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following preca utions: 1. maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. 2. electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. ground all fixtures and instruments, or protect with anti - static measures. 5. avoid the use of styrofoam or other highly static - prone materials for storage of completed board assemblies.
document number: 002 - 05091 rev.*a page 31 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 6.3 precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: 1. humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. 2. discharge of static electricity when high - v oltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. 3. corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. radiation, including cosmic radiation most devices are not designed for environm ents involving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. 5. smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in other special environmental conditions should consult with sales representatives.
document number: 002 - 05091 rev.*a page 32 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 7. h andling d evices power s upply p ins in products with multiple vcc and vss pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch - up. however, all of these pins should be connected externally to the power supply or ground lines in order to reduce ele ctromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with each power pins and gnd pins of this device at low impedance. it is also advisable that a ceramic capacitor of approximately 0.1 f be connected as a bypass capacitor between v cc and v ss , between avcc and avss and between avrh and avrl near this device. a malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the vcc power supply voltage. as a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in vcc ripple (peak - to - peak val ue) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the standard vcc value, and the transient fluctuation rate does not exceed 0.1 v/s at a momentary fluctuation such as switching the power supply. crystal o scillator c ircuit noise near th e x0 /x1 and x0a/ x1 a pins may cause the device to malfunction. design the printed circuit board so that x0 / x1, x0a/x1a pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. i t is strongly recommended that the pc board artwork be designed such that the x0/x1 and x0a/x1a pins are surrounded by ground plane as this is expected to produce stable operation. evaluate oscillation of your using crystal oscillator by your mount board. sub c rystal o scillator this series sub oscillator circuit is low gain to keep the low current consumption. the crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillatio n. ? surface mount type size: more than 3.2 mm 1.5 mm lo ad capacitance: approximately 6 pf to 7 pf when the standard setting (ccs/ccb=11001110) load capacitance: approximately 4 pf to 7 pf when the low power setting (ccs/ccb=00000100) ? lead type load capacitance: approximately 6 pf to 7 pf when the standard setting (ccs/ccb=11001110) load capacitance: approximately 4 pf to 7 pf when the low power setting (ccs/ccb=00000100)
document number: 002 - 05091 rev.*a page 33 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a using an e xternal c lock when using an external clock as an input of the main clock, set x0/x1 to the external clock input, and input the clock to x0. x1(pe3) can be used as a general - purpose i/o port. similarly, when using an external clock as an input of the sub clock, set x0a/x1a to the external clock input, and input the clock to x0a. x1a (p47) can be used as a general - purpose i/o port. handling when u sing multi - f unction s erial p in as i 2 c p in if it is using the multi - function serial pin as i 2 c pins, p - ch transistor of digital output is always disabled. however, i 2 c pins need to keep the electrical characteristic like other pins and not to connect to the external i 2 c bus system with power off. c pin this series contains the regulator. be sure to connect a smoothing capacitor (c s ) for the regulator between the c pin and the gnd pin. please use a ceram ic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. however, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (f characteristics and y5v characteristic s). please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. a smoothing capacitor of about 4.7 f would be recommended for this series. mode p ins (md0) connect the md pin (md0) directly to vcc or vss pins. design the printed circuit board such that the pull - up/down resistance stays low, as well as the distance between the mode pins and vcc pins or vss pi ns is as short as possible and the connection impedance is low, when the pins are pulled - up/down such as for switching the pin level and rewriting the flash memory data. it is because of preventing the device erroneously switching to test mode due to noise . device c vss c s gnd ? example of using an external clock device x0(x0a) x1 ( pe3 ), x1a ( p47) can be used as general - purpose i/o ports. set as external clock input
document number: 002 - 05091 rev.*a page 34 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a notes on p ower - on turn power on/off in the following order or at the same time. turning on : vbat vcc vcc avcc avrh vcc vbat avrh avcc vcc serial communication there is a possibility to receive wrong data due to the noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. if an erro r is detected , retransmit the data. differences in f eatures among the p roducts with d ifferent m emory s izes and between flash p roducts and mask p roducts the electric characteristics including power consumption, esd, latch - up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between flash products and mask products are different because chip layout and memory structures are different. if you are switching to use a different product of the same serie s, please make sure to evaluate the electric characteristics. pull - up f unction of 5v t olerant i/o please do not input the signal more than vcc voltage at the time of pull - up function use of 5v tolerant i/o.
document number: 002 - 05091 rev.*a page 35 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 8. b lock d iagram c o r t e x - m 0 + c o r e @ 4 0 m h z ( m a x ) f l a s h i / f c l o c k r e s e t g e n e r a t o r d u a l - t i m e r w a t c h d o g t i m e r ( h a r d w a r e ) d m a c 2 c h . c s v e x t e r n a l i n t e r r u p t c o n t r o l l e r 8 p i n + n m i p o w e r - o n r e s e t o n - c h i p s r a m 6 k b y t e a h b - a p b b r i d g e : a p b 1 ( m a x 4 0 m h z ) a h b - a p b b r i d g e : a p b 0 ( m a x 4 0 m h z ) c l k n v i c w a t c h d o g t i m e r ( s o f t w a r e ) s e c u r i t y 1 2 - b i t a / d c o n v e r t e r s w c l k , s w d i o x 0 a v c c , a v s s a n x x t i o a x t i o b x c x 1 x 0 a x 1 a s c k x s i n x s o t x i n t x n m i x p 0 x , p 1 x , . . . p x x i n i t x m o d e - c t r l i r q - m o n i t o r m d 0 r e g u l a t o r a h b - a h b b r i d g e o n - c h i p f l a s h 5 6 k b y t e / 8 8 k b y t e m u l t i - f u n c t i o n s e r i a l i / f 3 c h . ( w i t h f i f o ) g p i o p i n - f u n c t i o n - c t r l l v d m u l t i - l a y e r a h b ( m a x 4 0 m h z ) s w - d p m a i n o s c p l l s u b o s c c r 4 m h z c r 1 0 0 k h z l v d c t r l b a s e t i m e r 1 6 - b i t 4 c h . / 3 2 - b i t 2 c h . r e a l - t i m e c l o c k r t c c o , s u b o u t u n i t 0 q p r c 1 c h . a i n x b i n x z i n x m u l t i - f u n c t i o n t i m e r 1 6 - b i t f r e e - r u n t i m e r 3 c h . 1 6 - b i t o u t p u t c o m p a r e 6 c h . 1 6 - b i t i n p u t c a p t u r e 4 c h . w a v e f o r m g e n e r a t o r 3 c h . a / d a c t i v a t i o n c o m p a r e 6 c h . 1 6 - b i t p p g 3 c h . i c 0 x d t t i 0 x r t o 0 x f r c k x c r o u t s o u r c e c l o c k i g t r g x a d t g s c s x w a t c h c o u n t e r m o d e - c t r l p e r i p h e r a l c l o c k g a t i n g l o w - s p e e d c r p r e s c a l e r m t b s y s t e m r o m t a b l e b i t b a n d w r a p p e r f a s t g p i o t o p i n - f u n c t i o n - c t r l t o f a s t g p i o s 6 e 1 a 1 1 / s 6 e 1 a 1 2 a v r h ( o n l y 4 8 / 5 2 p i n p k g )
document number: 002 - 05091 rev.*a page 36 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 9. m emo ry s ize see memory size in 1 . p roduct l ineup to confirm the memory size. 10. m emory m ap memory map (1) f l a s h 0 x 0 0 0 0 _ 0 0 0 0 0 x 0 0 1 0 _ 0 0 0 0 0 x 2 0 0 0 _ 0 0 0 0 s r a m 0 x 2 0 0 8 _ 0 0 0 0 r e s e r v e d 0 x 2 2 0 0 _ 0 0 0 0 r e s e r v e d s e c u r i t y 3 2 m b y t e s b i t b a n d a l i a s 0 x 2 4 0 0 _ 0 0 0 0 r e s e r v e d 0 x 4 0 0 0 _ 0 0 0 0 p e r i p h e r a l s 0 x 4 2 0 0 _ 0 0 0 0 0 x e 0 0 0 _ 0 0 0 0 c o r t e x - m 0 + p r i v a t e p e r i p h e r a l s 0 x f 0 0 0 _ 0 0 0 0 r o m t a b l e 0 x f f f f _ f f f f 3 2 m b y t e s b i t b a n d a l i a s r e s e r v e d 0 x 4 4 0 0 _ 0 0 0 0 0 x 4 0 0 0 _ 0 0 0 0 0 x 4 1 f f _ f f f f f l a s h i / f 0 x 4 0 0 0 _ 1 0 0 0 0 x 4 0 0 1 _ 0 0 0 0 c l o c k / r e s e t 0 x 4 0 0 1 _ 2 0 0 0 0 x 4 0 0 1 _ 1 0 0 0 s w w d t h w w d t 0 x 4 0 0 1 _ 6 0 0 0 r e s e r v e d 0 x 4 0 0 1 _ 3 0 0 0 d u a l t i m e r r e s e r v e d 0 x 4 0 0 2 _ 0 0 0 0 p e r i p h e r a l a r e a 0 x 4 0 0 2 _ 1 0 0 0 p p g 0 x 4 0 0 2 _ 4 0 0 0 0 x 4 0 0 2 _ 5 0 0 0 b a s e t i m e r 0 x 4 0 0 2 _ 6 0 0 0 0 x 4 0 0 2 _ 7 0 0 0 a / d c 0 x 4 0 0 2 _ 8 0 0 0 q p r c 0 x 4 0 0 3 _ 0 0 0 0 e x t i 0 x 4 0 0 3 _ 1 0 0 0 i n t - r e q r e a d 0 x 4 0 0 3 _ 2 0 0 0 0 x 4 0 0 3 _ 3 0 0 0 0 x 4 0 0 3 _ 4 0 0 0 0 x 4 0 0 3 _ 5 0 0 0 0 x 4 0 0 3 _ 5 1 0 0 0 x 4 0 0 3 _ 8 0 0 0 m f s 0 x 4 0 0 3 _ 9 0 0 0 0 x 4 0 0 3 _ a 0 0 0 w a t c h c o u n t e r 0 x 4 0 0 3 _ b 0 0 0 0 x 4 0 0 3 _ c 1 0 0 l v d 0 x 4 0 0 6 _ 0 0 0 0 0 x 4 0 0 6 _ 1 0 0 0 d m a c r e s e r v e d 0 x 4 0 0 3 _ c 0 0 0 0 x 4 0 0 2 _ e 0 0 0 c r t r i m 0 x 4 0 0 2 _ f 0 0 0 0 x 0 0 1 0 _ 0 0 0 4 r t c c r t r i m 0 x 0 0 1 0 _ 0 0 0 8 0 x f 8 0 0 _ 0 0 0 0 f a s t g p i o ( s i n g l e - c y c l e i / o p o r t ) r e s e r v e d r e s e r v e d l o w s p e e d c r p r e s c a l e r r e s e r v e d g p i o r e s e r v e d r e s e r v e d r e s e r v e d m f t u n i t 0 r e s e r v e d 0 x 4 0 0 1 _ 5 0 0 0 0 x f 8 0 2 _ 0 0 0 0 r e s e r v e d r e s e r v e d r e s e r v e d p e r i p h e r a l c l o c k g a t i n g 0 x 4 0 0 3 _ c 8 0 0 m t b _ d w t m t b r e g i s t e r s ( s f r ) 0 x f 0 0 0 _ 1 0 0 0 0 x f 0 0 0 _ 2 0 0 0 0 x f 0 0 0 _ 3 0 0 0 r e s e r v e d s e e m e m o r y m a p ( 2 ) f o r t h e m e m o r y s i z e d e t a i l s . see " ? memory map(2)" for the memory size details.
document number: 002 - 05091 rev.*a page 37 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a memory map(2) s6e1a12b0a s6e1a12c0a s6e1a11b0a s6e1a11c0a 0x2008_0000 0x2008_0000 0x2000_1800 0x2000_1800 0x2000_0000 0x2000_0000 0x0010_0004 cr trimming 0x0010_0004 cr trimming 0x0010_0000 security 0x0010_0000 security 0x0001_6000 0x0000_e000 0x0000_0000 0x0000_0000 sram 6k bytes sram 6k bytes flash 88k bytes * reserved reserved reserved flash 56kbytes * reserved reserved reserved
document number: 002 - 05091 rev.*a page 38 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a peripheral address map start addre ss end address bus peripheral 0x4000_0000 0x4000_0fff ahb flash memory i/f register 0x4000_1000 0x4000_ffff reserved 0x4001_0000 0x4001_0fff apb0 clock/reset control 0x4001_1000 0x4001_1fff hardware watchdog t imer 0x4001_2000 0x4001_2fff software watchdog t imer 0x4001_3000 0x4001_4fff reserved 0x4001_5000 0x4001_5fff dual - timer 0x4001_6000 0x4001_ffff reserved 0x4002_0000 0x4002_0fff apb1 multi - function t imer unit 0 0x4002_1000 0x4002_3fff reserved 0x4002_4000 0x4002_4fff ppg 0x4002_5000 0x4002_5fff base timer 0x4002_6000 0x4002_6fff q uadrature position/revolution counter 0x4002_7000 0x4002_7fff a/d converter 0x4002_8000 0x4002_dfff reserved 0x4002_e000 0x4002_efff built - in cr trimming 0x4002_f000 0x4002_ffff reserved 0x4003_0000 0x4003_0fff external interrupt controller 0x4003_1000 0x4003_1fff interrupt request batch - read function 0x4003_2000 0x4003_2fff reserved 0x4003_3000 0x4003_3fff gpio 0x4003_4000 0x4003_4fff reserved 0x4003_5000 0x4003_57ff low - voltage detection 0x4003_5800 0x4003_7fff reserved 0x4003_8000 0x4003_8fff multi - function s erial interface 0x4003_9000 0x4003_9fff r eserved 0x4003_a000 0x4003_afff watch counter 0x4003_b000 0x4003_bfff r eal - time clock 0x4003_c000 0x4003_c 0 ff low - speed cr prescaler 0x4003_c100 0x4003_c7ff peripheral clock gating 0x4003_ c8 00 0x4003_ f fff reserved 0x4004_0000 0x4005_ffff ahb reserved 0x4006_0000 0x4006_0fff dmac register 0x4006_1000 0x 41ff _ffff reserved
document number: 002 - 05091 rev.*a page 39 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 11. p in s tatus i n e ach cpu s tate the terms used for pin status have the following meanings. ? initx=0 this is the period when the initx pin is the l level. ? initx=1 this is the period when the initx pin is the h level. ? spl=0 this is the status that the standby pin l evel setting bit (spl) in the standby mode control register (stb_ctl) is set to 0. ? spl=1 this is the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to 1. ? input enabled indicates that the input function can be used. ? internal input fixed at 0 this is the status that the input function cannot be used. internal input is fixed at l. ? hi - z indicates that the pin drive transistor is disabled and the pin is put in the hi - z state. ? setting disabled indicat es that the setting is disabled. ? maintain previous state maintains the state that was immediately prior to entering the current mode. if a built - in peripheral function is operating, the output follows the peripheral function. if the pin is being used as a port, that output is maintained. ? analog input is enabled indicates that the analog input is enabled.
document number: 002 - 05091 rev.*a page 40 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a list of pin status pin status type function group state upon p ower - on reset or low - voltage detection state at initx input state upon d evice internal reset state in run mode or sleep mode state in t imer mode , rtc mode , or stop mode power supply unstable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 a gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" main crystal oscillator input pin/ external main clock input selected input enabled input enabled input enabled input enabled input enabled input enabled b gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" external main clock input selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" main crystal oscillator output pin hi - z / internal input fixed at "0" / i nput enable d hi - z / internal input fixed at "0" hi - z / internal input fixed at "0" maintain previous state/when oscillation stop s * 1 , hi - z / internal input fixed at "0" maintain previous state/when oscillation stop s * 1 , hi - z / internal input fixed at "0" maintain previous state/when oscillation stop s * 1 , hi - z / internal inpu t fixed at "0" c initx input pin pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled d mode input pin input enabled input enabled input enabled input enabled input enabled input enabled e gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" sub crystal oscillator input pin / external sub clock input selected input enabled input enabled input enabled input enabled input enabled input enabled f gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" external sub clock input selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0"
document number: 002 - 05091 rev.*a page 41 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a pin status type function group state upon p ower - on reset or low - voltage detection state at initx input state upon d evice internal reset state in run mode or sleep mode state in t imer mode , rtc mode , or stop mode power supply unstable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 sub crystal oscillator output pin hi - z / internal input fixed at " 0 " / i nput enable d hi - z / internal input fixed at "0" hi - z / internal input fixed at "0" maintain previous state maintain previous state /when oscillation stop s * 2 , hi - z / internal input fixed at "0" maintain previous state /when oscillation stop s * 2 , hi - z / internal input fixed at "0" g nmix selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state resource other than the above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at "0" gpio selected h serial wire debug selected hi - z pull - up / input enabled pull - up / input enabled maintain previous state maintain previous state maintain previous state gpio selected setting disabled setting disabled setting disabled hi - z / internal input fixed at "0" i resource selected hi - z hi - z / input enabled hi - z / input enabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected j external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state resource other than the above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at "0" gpio selected k analog input selected hi - z hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enab led hi - z / internal input fixed at "0" / analog input enabled resource other than the above selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected l analog input selected hi - z hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled
document number: 002 - 05091 rev.*a page 42 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a pin status type function group state upon p ower - on reset or low - voltage detection state at initx input state upon d evice internal reset state in run mode or sleep mode state in t imer mode , rtc mode , or stop mode power supply unstable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state resource other than the above selected hi - z / internal input fixed at "0" gpio selected *1:oscillation stops in s ub timer mode , low - speed cr timer mode, stop mode, rtc mode. *2: oscillation stop s in stop mode.
document number: 002 - 05091 rev.*a page 43 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12. e lectrical c haracteristics 12.1 absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage* 1, * 2 v cc v ss - 0.5 v ss + 6.5 v analog power supply voltage * 1, * 3 av cc v ss - 0.5 v ss + 6.5 v analog reference voltage* 1, * 3 avrh v ss - 0.5 v ss + 6.5 v only s6e1a1xc0a input voltage* 1 v i v ss - 0.5 v cc + 0.5 ( 6.5 v) v v ss - 0.5 v ss + 6.5 v 5v tolerant analog pin input voltage* 1 v ia v ss - 0.5 a v cc + 0.5 ( 6.5 v) v output voltage* 1 v o v ss - 0.5 vcc + 0.5 ( 6.5 v) v " l " level maximum output current* 4 i ol - 10 ma 4 ma type 20 ma 12 ma type " l " level average output current* 5 i olav - 4 ma 4 ma type 12 ma 12 ma type " l " level total maximum output current i ol - 100 ma " l " level total average output current* 6 i olav - 50 ma " h " level maximum output current* 4 i oh - - 10 ma 4 ma type - 20 ma 12 ma type " h " level average output current* 5 i ohav - - 4 ma 4 ma type - 12 ma 12 ma type " h " level total maximum output current i oh - - 100 ma " h " level total average output current* 6 i ohav - - 50 ma power consumption p d - 200 mw storage temperature t stg - 55 + 150 c *1: these parameters are based on the condition that v ss = a vss = 0 v. *2: v cc must not drop below v ss - 0.5 v. * 3 :ensure that the voltage does not to exceed v cc + 0. 5 v at power - on . * 4 : the maximum output current is the peak value for a single pin. * 5 : the average output is the average current for a single pin over a period of 100 ms. * 6 : the total average output current is the average current for all pins over a period of 100 ms. warning ? semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings
document number: 002 - 05091 rev.*a page 44 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.2 recommended operating conditions (v ss = a v ss = 0.0v) parameter symbol cond itions value unit remarks min max power supply voltage v cc - 2.7 * 2 5.5 v analog power supply voltage av cc - 2.7 5.5 v av cc = v cc analog reference voltage avrh - 2.7 av cc v only s6e1a1xc0a smoothing capacitor c s - 1 10 f 1 operating t emperature ta - - 40 + 105 c 1 : see "c pin" in " 6 . h andling p recautions " for the connection of the smoothing capacitor. *2: in between less than the m inimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built - in high - speed cr(including main pll is used) or built - in low - speed cr is possible to operate only. warning 1. the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated within these ranges. 2. always use semicond uctor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. 3. no warranty is made with respect to uses, operating conditions, or combinations not repre sented on the data sheet. 4. users considering application outside the listed conditions are advised to contact their representatives beforehand.
document number: 002 - 05091 rev.*a page 45 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.3 dc characteristics 12.3.1 current rating symbol (pin name) conditions hclk frequency * 4 value unit remarks typ * 1 max * 2 icc (vcc) r un mode , code executed from flash 4mhz e xternal clock input , pll on* 8 nop code executed built - in high speed cr stopped all p eripheral clock stopped by ckenx 4mhz 0.7 1.5 ma *3 8mhz 1.3 2.3 20mhz 2.8 4.0 40mhz 5.7 7.3 4mhz e xternal clock input , pll on* 8 benchmark code executed built - in high speed cr stopped pclk1 stopped 4mhz 0.6 1.4 ma *3 8mhz 1.2 2.1 20mhz 2.6 3.7 40mhz 4.8 6.3 4mhz c rystal oscillation , pll on* 8 nop code executed built - in high speed cr stopped all p eripheral clock stopped by ckenx 4mhz 1.0 2.9 ma *3 8mhz 1.7 3.6 20mhz 3.4 5.6 40mhz 5.7 8.2 r un mode , code executed from ram 4mhz e xternal clock input , pll on* 8 nop code executed built - in high speed cr stopped all p eripheral clock stopped by ckenx 4mhz 0.5 1.2 ma *3 8mhz 0.9 1.8 20mhz 2.0 2.9 40mhz 3.7 4.8 r un mode , code executed from flash 4mhz e xternal clock input , pll on nop code executed built - in high speed cr stopped pclk1 stopped 40mhz 2.8 3.7 ma *3 ,*6,*7 r un mode , code executed from flash built - in h igh speed cr * 5 nop code executed all p eripheral clock stopped by ckenx 4mhz 0.8 1.5 ma *3 32khz c rystal oscillation nop code executed all p eripheral clock stopped by ckenx 32khz 65 900 a *3 built - in low speed cr nop code executed all p eripheral clock stopped by ckenx 100khz 73 920 a *3 iccs (vcc) sleep operation 4mhz e xternal clock input , pll on* 8 all p eripheral clock stopped by ckenx 4mhz 0.4 1.2 ma *3 8mhz 0.7 1.6 20mhz 1.5 2.4 40mhz 2.7 3.7 built - in h igh speed cr * 5 all p eripheral clock stopped by ckenx 4mhz 0.5 1.2 ma *3 32khz c rystal oscillation all p eripheral clock stopped by ckenx 32khz 63 880 a *3 built - in low speed cr all p eripheral clock stopped by ckenx 100khz 66 890 a *3
document number: 002 - 05091 rev.*a page 46 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a *1 : ta=+25 ,v cc =3. 0 v *2 : ta=+105 ,v cc =5.5v *3 : all ports are fixed *4 : pclk0 =hclk/8 *5 : the frequency is set to 4mhz by trimming *6 : flash sync down is set to frwtr.rwt = 11 and fsyndn.sd = 1111 *7 : v cc = 2.7 v *8 : when hclk=4mhz, pll off symbol (pin name) conditions value uni t remarks typ max i cch (vcc) stop mode ta=25 cct (vcc) sub timer mode ta=25 ccr (vcc) rtc mode ta=25
document number: 002 - 05091 rev.*a page 47 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a lvd current ( v cc = 2.7v to 5.5v, v ss = a v ss = 0v, ta = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks typ max low - v oltage detection circuit (lvd) power supply current i cclvd vcc at operation 0.13 0.3 flash memory current ( v cc = 2.7v to 5.5v, v ss = a v ss = 0v, ta = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks typ max flash m emory w rite/ e rase current i ccflash vcc at write/erase 9.5 11.2 ma a/d convertor current ( s6e1a1xc0a) ( v cc = 2.7v to 5.5v, v ss = a v ss = 0v, ta = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks typ max power supply current i ccad avcc at operation 0.7 0.9 ma at stop 0.13 13 ccavrh avrh at operation 1.1 1.97 ma avrh=5.5v at stop 0.1 1.7 a/d convertor current ( s6e1a1xb0a) ( v cc = 2.7v to 5.5v, v ss = a v ss = 0v, ta = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks typ max power supply current i ccad avcc at operation 1.8 2.87 ma at stop 0.23 14.7 a peripheral current dissipation clock system peripheral conditions frequency (mhz) unit remarks 4 8 20 40 hclk gpio at all ports operation 0.11 0.22 0.55 1.10 ma dmac at 2ch operation 0.05 0.11 0.25 0.51 pclk1 base timer at 4ch operation 0.03 0.05 0.15 0.30 ma multi - functional timer/ppg at 1unit/4ch operation 0.14 0.28 0.68 1.38 quadrature position/revolution counter at 1unit operation 0.02 0.04 0.11 0.22 adc at 1unit operation 0.07 0.14 0.37 0.73 multi - function serial at 1ch operation 0.15 0.31 0.77 1.54
document number: 002 - 05091 rev.*a page 48 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.3.2 pin characteristics (v cc = a v cc = 2.7 v to 5.5 v, v ss = a v ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min typ max "h" level input voltage (hysteresis input) v ihs cmos hysteresis input pin, md0, pe0 - v cc 0.8 - v cc + 0.3 v 5v tolerant input pin - v cc 0.8 - v ss + 5.5 v "l" level input voltage (hysteresis input) v ils cmos hysteresis input pin, md0, pe0 - v ss - 0.3 - v cc 0.2 v 5v tolerant input pin - v ss - 0.3 - v cc 0.2 v "h" level output voltage v oh 4 ma type v cc oh = - 4 ma v cc - 0.5 - v cc v v cc < 4.5 v , i oh = - 2 ma 12 ma type v cc oh = - 12 ma v cc - 0.5 - v cc v v cc < 4.5 v , i oh = - 8 ma "l" level output voltage v ol 4 ma type v cc ol = 4 ma v ss - 0.4 v v cc < 4.5 v , i ol = 2 ma 12 ma type v cc ol = 12 ma v ss - 0.4 v v cc < 4.5 v , i ol = 8 ma input leak current i il - - - 5 - + 5 pu pull - up pin v cc cc < 4.5 v - - 180 input capacitance c in other than vcc, vss, avcc, avss, avrh - - 5 15 pf
document number: 002 - 05091 rev.*a page 49 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.4 ac characteristics 12.4.1 main clock input characteristics (v cc = a v cc = 2.7 v to 5.5 v, v ss = a v ss = 0 v, ta = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks min max input frequency f ch x0, x1 v cc cc < 4.5v 4 20 - 4 4 0 mhz when the external c lock is used input clock cycle t cylh - 25 250 ns when the external c lock is used input clock pulse width - p wh /t cylh , p wl /t cylh 45 55 % when the external c lock is used input clock ris ing time and fall ing time t cf, t cr - - 5 ns when the external c lock is used internal operating c lock *1 frequency f cm - - - 41.2 mhz master clock f cc - - - 41.2 mhz base clock (hclk/fclk) f cp0 - - - 41.2 mhz apb0 bus clock* 2 f cp1 - - - 41.2 mhz apb1 bus clock* 2 internal operating clock *1 cycle time t cycc - - 24.27 - ns base clock (hclk/fclk) t cycp0 - - 24.27 - ns apb0 bus clock* 2 t cycp1 - - 24.27 - ns apb1 bus clock* 2 *1: for details of each internal operating clock , refer to " c hapter : clock " in " fm 0 + family peripheral manual ". *2: for details of the apb bus to which a peripheral is connected , see " 8 . b lock d iagram ". x0
document number: 002 - 05091 rev.*a page 50 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.4.2 sub clock input characteristics (v cc = a v cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min typ max input frequency 1/t cyll x0a, x1a - - 32.768 - khz when the crystal oscillator is connected - 32 - 100 khz when the external c lock is used input clock cycle t cyll - 10 - 31.25 wh /t cyll , p wl /t cyll 45 - 55 % when the external c lock is used *: see " s ub crystal oscillator " in " 7 . h andling d evices " for the crystal oscillator used. x0 a
document number: 002 - 05091 rev.*a page 51 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.4.3 built - in cr oscillation characteristics built - in high - speed cr (v cc = a v cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol conditions value unit remarks min typ max clock frequency f crh ta = + 25 c , 3.6v < v cc *1 ta =0 c to + 8 5 c , 3.6v < v cc cc cc cc cc cc crwt - - - 30 built - in low - speed cr (v cc = a v cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol conditions value unit remarks min typ max clock frequency f crl - 50 100 150 k hz
document number: 002 - 05091 rev.*a page 52 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.4.4 operating conditions of main pll ( in the case of using the main clock as the input clock of the pll ) (v cc = av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time* 1 (lock up time) t lock 100 - - plli 4 - 16 mh z pll multiple rate - 5 - 37 multiple pll macro oscillation clock frequency f pllo 75 - 150 mh z main pll clock frequency* 2 f clkpll - - 40 mh z * 1 : the wait time is the time it takes for pll oscillation to stabilize. *2: for details of the main pll clock (clkpll), refer to "c hapter : clock" in "fm0+ family peripheral manual". 12.4.5 operating conditions of main pll (in the case of using the built - in high - speed cr clock as the input clock of the main pll) (v cc = av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time* 1 (lock up time) t lock 100 - - plli 3.88 4 4.12 mh z pll multiple rate - 19 - 35 multiple pll macro oscillation clock frequency f pllo 72 - 150 mh z main pll clock frequency* 2 f clkpll - - 41.2 mh z * 1 : the wait time is the time it takes for pll oscillation to stabilize. *2: for details of the main pll clock (clkpll), refer to "c hapter : clock" in "fm0+ family peripheral manual". note: for the main pll source clock, i npu t the high - speed cr clock (clkhc) whose frequency has been trimme d.
document number: 002 - 05091 rev.*a page 53 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.4.6 reset input characteristics (v cc = av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max reset input time t initx initx - 500 - ns 12.4.7 power - on reset timing (v cc = av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol pin name value unit remarks min max power supply rising time tr v cc 0 - ms power supply shut down time toff 1 - ms time until releasing power - on reset tprt 0.43 3.4 ms glossary ? vcc_minimum : minimum v cc of recommended operating conditions . ? vdh _minimum : minimum release voltage (when svhr=0000) of low - v oltage detection reset . see " 6. low - v oltage detection characteristics " . 0 . 2 v v d h _ m i n i m u m v c c _ m i n i m u m t p r t i n t e r n a l r s t v c c c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e t r 0 . 2 v 0 . 2 v t o f f
document number: 002 - 05091 rev.*a page 54 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.4.8 base timer input timing timer input timing (v cc = av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh , t tiwl tioan/tiobn (when using as eck, tin) - 2 t cycp - ns trigger input timing (v cc = av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t trgh , t trgl tioan /tiobn (when using as tgin) - 2 t cycp - ns note: ? t cycp indicates the apb bus clock cycle time. for the number of the apb bus to which the base timer has been connected , see " 8 . b lock d iagram ". eck tin tgin t tiwh v ihs v ihs v ils v ils t tiw l t trgh v ihs v ihs v ils v ils t trg l
document number: 002 - 05091 rev.*a page 55 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.4.9 csio timing synchronous serial (spi = 0, scinv = 0) (v cc = av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max serial clock cycle time t scyc sck x internal shift clock operation 4 t cycp - 4 t cycp - ns sck sot delay time slovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time ivshi sckx , sinx 50 - 30 - ns sck sin hold shixi sckx , sinx 0 - 0 - ns serial clock "l" pulse width t slsh sckx external shift clock operation 2 t cycp - 10 - 2 t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time slove sckx , sotx - 50 - 30 ns sin sck setup time ivshe sckx , sinx 10 - 10 - ns sck sin hold time shixe sckx , sinx 20 - 20 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes : ? the above ac characteristics are for clk synchronous mode. ? t cycp represents the apb bus clock cycle time. for the number of the apb bus to which multi - function serial has been connected, see " 8 . b lock d iagram ". ? the characteristics are only applicable when the relocate port numbers are the same. for instance, they are not applicable for the combination of sclkx_0 and sotx_1. ? external load capacitance c l = 30 pf ms bit = 0 sot sin sck t scyc v oh v oh v ol v ol v ol v ih v il v ih v il t slovi t ivshi t shixi
document number: 002 - 05091 rev.*a page 56 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a ms bit = 1 synchronous serial (spi = 0, scinv = 1 ) (v cc = av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol pin name conditions v cc < 4.5v v cc 4.5v unit min max min max serial clock cycle time t scyc sckx internal shift clock operation 4 t cycp - 4 t cycp - ns sck sot delay time shovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time ivsli sckx , sinx 50 - 30 - ns sck sin hold time slixi sckx , sinx 0 - 0 - ns serial clock "l" pulse width t slsh sckx external shift clock operation 2 t cycp - 10 - 2 t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time shove sckx , sotx - 50 - 30 ns sin sck setup time ivsle sckx , sinx 10 - 10 - ns sck sin hold time slixe sckx , sinx 20 - 20 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes : ? the above ac characteristics are for clk synchronous mode. ? t cycp represents the apb bus clock cycle time. for the number of the apb bus to which multi - function serial has been connected, see " 8 . b lock d iagram ". ? the characteristics ar e only applicable when the relocate port numbers are the same. for instance, they are not applicable for the combination of sclkx_0 and sotx_1. ? external load capacitance c l = 30 pf sck sin sot t slsh t shsl v ih t f tr v ih v oh v ih v il v il v ol v ih v il v ih v il t slove t ivshe t shixe
document number: 002 - 05091 rev.*a page 57 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a ms bit = 0 ms bit = 1 sot sin sck sck sin sot t scyc v oh v oh v oh v ol v ol v ih v il v ih v il t shovi t ivsli t slixi t shsl t slsh v ih tf tr v ih v oh v il v il v il v ol v ih v il v ih v il t shove t ivsle t slixe
document number: 002 - 05091 rev.*a page 58 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a synchronous serial (spi = 1, scinv = 0 ) (v cc = av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max serial clock cycle time t scyc sckx internal shift clock operation 4 t cycp - 4 t cycp - ns sck sot delay time shovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time ivsli sckx , sinx 50 - 30 - ns sck sin hold time slixi sckx , sinx 0 - 0 - ns sot sck delay time sovli sckx , sotx 2 t cycp - 30 - 2 t cycp - 30 - ns serial clock "l" pulse width t slsh sckx external shift clock operation 2 t cycp - 10 - 2 t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time shove sckx , s ot x - 50 - 30 ns sin sck setup time ivsle sckx , sinx 10 - 10 - ns sck sin hold time slixe sckx , sinx 20 - 20 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes : ? the above ac characteristics are for clk synchronous mode. ? t cycp represents the apb bus clock cycle time. for the number of the apb bus to which multi - function serial has been connected, see " 8 . b lock d iagram ". ? the characteristics are only applicable when the relocate port numbers are the same. for instance, they are not applicable for the combination of sclkx_0 and sotx_1. ? external load capacitance c l = 30 pf
document number: 002 - 05091 rev.*a page 59 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a ms bit = 0 ms bit = 1 *: this changes as data is written to the tdr register . sot sin sck sot sck sin t sovli t scyc t shovi v ol v ol v oh v oh v ol v oh v ol v ih v il v ih v il t ivsli t slixi tf tr t slsh t shsl t shove v il v il v ih v ih v ih v oh * v ol v oh v ol v ih v il v ih v il t ivsle t slixe
document number: 002 - 05091 rev.*a page 60 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a synchronous serial (spi = 1, scinv = 1 ) (v cc = av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max serial clock cycle time t scyc sckx internal shift clock operation 4 t cycp - 4 t cycp - ns sck sot delay time slovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time ivshi sckx , sinx 50 - 30 - ns sck sin hold time shixi sckx , sinx 0 - 0 - ns sot sck delay time sovhi sckx , sotx 2 t cycp - 30 - 2 t cycp - 30 - ns serial clock "l" pulse width t slsh sckx external shift clock operation 2 t cycp - 10 - 2 t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time slove sckx , s ot x - 50 - 30 ns sin sck setup time ivshe sckx , sinx 10 - 10 - ns sck shixe sckx , sinx 20 - 20 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes : ? the above ac characteristics are for clk synchronous mode. ? t cycp represents the apb bus clock cycle time. for the number of the apb bus to which multi - function serial has been connected, see " 8 . b lock d iagram ". ? the characteristics are only applicable when the relocate port numbers are the same. for instance, they are not applicable for the combination of sclkx_0 and sotx_1. ? external load capacitance c l = 30 pf
document number: 002 - 05091 rev.*a page 61 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a ms bit = 0 ms bit = 1 sot sin sck sck sin sot t scyc t slovi v ol v oh v oh v oh v ol v oh v ol v ih v il v ih v il t ivshi t shixi t sovhi t shsl tr t slsh tf t slove v il v il v il v ih v ih v ih v oh v ol v oh v ol v ih v il v ih v il t ivshe t shixe
document number: 002 - 05091 rev.*a page 62 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a when using synchronous serial chip select (spi = 1 , scinv = 0 , ms=0, cslvl=1 ) (v cc = 2.7v to 5.5v, v ss = 0v ) parameter symbol conditions v cc < 4.5v v cc 4.5v unit min max min max scs cssi internal shift clock operation (*1) - 5 0 (*1)+0 (*1) - 5 0 (*1)+0 ns sck hold time cshi (*2)+0 (*2)+ 5 0 (*2)+0 (*2)+ 5 0 ns scs deselect time t csdi (*3) - 5 0 +5t cycp (*3)+ 5 0 +5t cycp (*3) - 5 0 +5t cycp (*3)+ 5 0 +5t cycp ns scs csse external shift clock operation 3t cycp + 30 - 3t cycp + 30 - ns sck hold time cshe 0 - 0 - ns scs deselect time t csde 3t cycp + 30 - 3t cycp + 30 - ns scs dse - 40 - 40 ns scs dee 0 - 0 - ns (*1) : cssu bit value serial chip select timing operating clock cycle [ns] (*2) : cshd bit value serial chip select timing operating clock cycle [ns] (*3) : csds bit value serial chip select timing operating clock cycle [ns] notes : ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to, see " 8 . b lock d iagram ". ? about cssu, cshd, csds, serial chip select timing operating clock, see "fm0+ family peripheral manual". ? when the external load capacitance c l = 30pf.
document number: 002 - 05091 rev.*a page 63 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a scs output sck output sot (spi=0) sot (spi=1) scs input sck input sot (spi=0) sot (spi=1) t c ss i t c s h i t c s d i t c ss e t c s h e t c s d e t d e e t d s e
document number: 002 - 05091 rev.*a page 64 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a when using synchronous serial chip select (spi = 1 , scinv = 1, ms=0, cslvl=1 ) (v cc = 2.7v to 5.5v, v ss = 0v ) parameter symbol conditions v cc < 4.5v v cc 4.5v unit min max min max scs cssi internal shift clock operation (*1) - 5 0 (*1)+0 (*1) - 5 0 (*1)+0 ns sck hold time cshi (*2)+0 (*2)+ 5 0 (*2)+0 (*2)+ 5 0 ns scs deselect time t csdi (*3) - 5 0 +5t cycp (*3)+ 5 0 +5t cycp (*3) - 5 0 +5t cycp (*3)+ 5 0 +5t cycp ns scs csse external shift clock operation 3t cycp + 30 - 3t cycp + 30 - ns sck hold time cshe 0 - 0 - ns scs deselect time t csde 3t cycp + 30 - 3t cycp + 30 - ns scs dse - 40 - 40 ns scs dee 0 - 0 - ns (*1) : cssu bit value serial chip select timing operating clock cycle [ns] (*2) : cshd bit value serial chip select timing operating clock cycle [ns] (*3) : csds bit value serial chip select timing operating clock cycle [ns] notes : ? t cycp indicates the apb bus clock cycle tim e. about the apb bus number which multi - function serial is connected to, see " 8 . b lock d iagram ". ? about cssu, cshd, csds, serial chip select timing operating clock, see "fm0+ family peripheral manual". ? when the external load capacitance c l = 30pf.
document number: 002 - 05091 rev.*a page 65 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a scs output sck output sot (spi=0) sot (spi=1) scs input sck input sot (spi=0) sot (spi=1) t c ss i t c s h i t c s d i t c ss e t c s h e t c s d e t d e e t d s e
document number: 002 - 05091 rev.*a page 66 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a when using synchronous serial chip select (spi = 1 , scinv = 0, ms=0, cslvl=0 ) (v cc = 2.7v to 5.5v, v ss = 0v ) parameter symbol conditions v cc < 4.5v v cc 4.5v unit min max min max scs cssi internal shift clock operation (*1) - 5 0 (*1)+0 (*1) - 5 0 (*1)+0 ns sck hold time cshi (*2)+0 (*2)+ 5 0 (*2)+0 (*2)+ 5 0 ns scs deselect time t csdi (*3) - 5 0 +5t cycp (*3)+ 5 0 +5t cycp (*3) - 5 0 +5t cycp (*3)+ 5 0 +5t cycp ns scs csse external shift clock operation 3t cycp + 30 - 3t cycp + 30 - ns sck hold time cshe 0 - 0 - ns scs deselect time t csde 3t cycp + 30 - 3t cycp + 30 - ns scs dse - 40 - 40 ns scs dee 0 - 0 - ns (*1) : cssu bit value serial chip select timing operating clock cycle [ns] (*2) : cshd bit value serial chip select timing operating clock cycle [ns] (*3) : csds bit value serial chip select timing operating clock cycle [ns] notes : ? t cycp indicates the apb bus clock cycle tim e. about the apb bus number which multi - function serial is connected to, see " 8 . b lock d iagram ". ? about cssu, cshd, csds, serial chip select timing operating clock, see "fm0+ family peripheral manual". ? when the external load capacitance c l = 30pf.
document number: 002 - 05091 rev.*a page 67 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a scs output sck output sot (spi=0) sot (spi=1) scs input sck input sot (spi=0) sot (spi=1) t c ss i t c s h i t c s d i t csse t cshe t csde t dee t dse
document number: 002 - 05091 rev.*a page 68 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a when using synchronous serial chip select (spi = 1 , scinv = 1, ms=0, cslvl=0 ) (v cc = 2.7v to 5.5v, v ss = 0v ) parameter symbol conditions v cc < 4.5v v cc 4.5v unit min max min max scs cssi internal shift clock operation (*1) - 5 0 (*1)+0 (*1) - 5 0 (*1)+0 ns sck hold time cshi (*2)+0 (*2)+ 5 0 (*2)+0 (*2)+ 5 0 ns scs deselect time t csdi (*3) - 5 0 +5t cycp (*3)+ 5 0 +5t cycp (*3) - 5 0 +5t cycp (*3)+ 5 0 +5t cycp ns scs csse external shift clock operation 3t cycp + 30 - 3t cycp + 30 - ns sck hold time cshe 0 - 0 - ns scs deselect time t csde 3t cycp + 30 - 3t cycp + 30 - ns scs dse - 40 - 40 ns scs dee 0 - 0 - ns (*1) : cssu bit value serial chip select timing operating clock cycle [ns] (*2) : cshd bit value serial chip select timing operating clock cycle [ns] (*3) : csds bit value serial chip select timing operating clock cycle [ns] notes : ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to, see " 8 . b lock d iagram ". ? about cssu, cshd, csds, serial chip select timing operating clock, see "fm0+ family peripheral manual". ? when the external load capacitance c l = 30pf.
document number: 002 - 05091 rev.*a page 69 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a scs output sck output sot (spi=0) sot (spi=1) scs input sck input sot (spi=0) sot (spi=1) t c ss i t c s h i t c s d i t csse t cshe t csde t dee t dse
document number: 002 - 05091 rev.*a page 70 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a external clock (ext = 1 ) : asynchronous only (v cc = av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol conditions value unit remarks min max serial clock " l" pulse width t slsh c l = 30 pf t cycp + 10 - ns serial clock " h" pulse width t shsl t cycp + 10 - ns sck falling time tf - 5 ns sck rising time tr - 5 ns s ck t shsl v i l v i l v i l v ih v ih v ih tr tf t slsh
document number: 002 - 05091 rev.*a page 71 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.4.10 external input timing (v cc = av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t inh, t inl adtg x - 2 t cycp * 1 - ns a/d converter trigger input frckx free - run timer input clock icxx input capture dttixx - 2 t cycp * 1 - ns wave form generator int xx , nmix - 2 t cycp + 100 * 1 - ns external interrupt , nmi 500 * 2 - ns *1: t cycp represents the apb bus clock cycle time except when the apb bus clock stops in stop mode or in timer mode. for the number of the apb bus to which the multi - function timer is connected and that of the apb bus to which the external interrupt controller is c onnected, see " 8 . b lock d iagram ". *2: in stop mode and timer mode
document number: 002 - 05091 rev.*a page 72 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.4.11 q prc timing (v cc = av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol conditions value unit min max ain pin "h" width t ahl - 2 t cycp * - ns ain pin "l" width t all - bin pin "h" width t bhl - bin pin "l" width t bll - t ime from ain pin "h" level to bin rise t aubu pc_mode2 or pc_ m ode3 t ime from bin pin "h" level to ain fall t buad pc_mode2 or pc_mode3 t ime from ain pin "l" level to bin fall t adbd pc_mode2 or pc_mode3 t ime from bin pin "l" level to ain rise t bdau pc_mode2 or pc_mode3 t ime from bin pin "h" level to ain rise t buau pc_mode2 or pc_mode3 t ime from ain pin "h" level to bin fall t aubd pc_mode2 or pc_mode3 t ime from bin pin "l" level to ain fall t bdad pc_mode2 or pc_mode3 t ime from ain pin "l" level to bin rise t adbu pc_mode2 or pc_mode3 zin pin "h" width t zhl qcr:cgsc="0" zin pin "l" width t zll qcr:cgsc="0" time from determined zin level to ain/bin rise and fall t zabe qcr:cgsc="1" time from ain/bin rise and fall time to determined zin level t abez qcr:cgsc="1" *: t cycp represents the apb bus clock cycle time except when the apb bus clock stops in stop mode or in timer mode. for the number of the apb bus to which the qprc is connected, see " 8 . b lock d iagram ". ain bin t aubu t buad t adbd t bdau t ahl t all t bhl t bll
document number: 002 - 05091 rev.*a page 73 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a zin ain/bin zin bin t buau t aubd t bdad t adbu t bhl t bll t ahl t all ain
document number: 002 - 05091 rev.*a page 74 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.4.12 i 2 c timing (v cc = av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol conditions standard - mode fast - mode unit remarks min max min max scl clock frequency f scl c l = 30 pf, r = (vp/i ol ) * 1 0 100 0 400 khz (repeated) start condition hold time sda scl hdsta 4.0 - 0.6 - low 4.7 - 1.3 - high 4.0 - 0.6 - scl sda susta 4.7 - 0.6 - scl sda hddat 0 3.45* 2 0 0.9* 3 sda scl sudat 250 - 100 - ns stop condition setup time scl sda susto 4.0 - 0.6 - buf 4.7 - 1.3 - sp - 2 t cycp * 4 - 2 t cycp * 4 - ns *1: r represent s the pull - up resistance of the scl and sda lines , and c l the load capacitance of the scl and sda lines. vp represents the power supply voltage of the pull - up resistance , and i ol the v ol guaranteed current. *2: the maximum t hddat must satisfy at least the condition that the period during which the device is holding the scl signal at "l" (t low ) does not extend. *3: a fast - mode i 2 c bus device can be used in a s tandard - mode i 2 c bus system , provided that t he condition of "t sudat 250 ns" is fulfilled. *4: t cycp represents the apb bus clock cycle time. for the number of the apb bus to which the i 2 c is connected, see " 8 . b lock d iagram ". to use standard - mode, set the apb bus clock at 2mhz or more. to use fast - mode, s et the apb bus clock at 8 mhz or more. s cl sda
document number: 002 - 05091 rev.*a page 75 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.4.13 sw - dp timing (v cc = av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max swdio setup time t s ws sw c l k, swdio - 15 - ns swdio hold time t sw h sw c l k, swdio - 15 - ns swdio delay time t sw d swclk, swdio - - 45 ns note: ? external load capacitance c l = 30 pf swdio (when input) swclk swdio (when output) sw d
document number: 002 - 05091 rev.*a page 76 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.5 12 - bit a/d converter electrical characteristics of a/d c onverter (v cc = av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v, ta = - 40c to + 105 c) parameter symbol pin name value unit remarks min typ max resolution - - - - 12 bit integral nonl inearity - - - 4.5 - 4.5 lsb differential non linearity - - - 2.5 - + 2.5 lsb zero transition voltage v z t an xx - 20 - + 20 mv full - scale transition voltage v fst an xx avrh - 20 - avrh+ 20 mv s6e1a1xc0a av cc - 20 - av cc +20 s6e1a1xb0a conversion time - - 0.8 * 1 - - - - cc 1 s6e1a1xb0a sampling time * 2 ts - 0.24 - 10 cc cc < 4.5v 0.6 s6e1a1xb0a compare clock cycle* 3 tcck - 40 - 1000 ns s6e1a1xc0a a v cc cc < 4.5v 100 s6e1a1xb0a state transition time to operation permission tstt - - - 1.0 ain - - - 9.7 pf analog input resistance r ain - - - 1. 6 k cc cc < 4.5v interchannel disparity - - - - 4 lsb analog port input current - an xx - - 5 ss - avrh v s6e1a1xc0a a v ss - a v cc s6e1a1xb0a reference voltage - avrh 2.7 - a v cc v only s6e1a1xb0a *1: the c onversion time is the value of "sampling time (ts) + compare time (tc)". the minimum conversion time is computed according to the following conditions: sampling time = 240 ns , compare time = 560 n s ( a vcc 4.5 v). must be set 25mhz to the base clock (hclk). ensure that the conversion time satisfies the specifications of the sampling time (ts) and compare clock cycle (tcck). for details of the settings of the sampling time and co mpare clock cycle, refer to " c hapter : a/d converter " in " fm0+ family peripheral manual analog macro part ". the register setting s of the a / d c onverter are reflected in the operation according to the apb bus clock timing. for the number of the apb bus to which the a/d converter is connected, see " 8 . b lock d iagram ". the base cloc k (hclk) is used to generate the sampling time and the compare clock cycle. *2: the required sampling time varies according to the external impedance. set a sampling time that satisfies ( equation 1 ). *3: the compare time ( tc ) is the result of ( equation 2).
document number: 002 - 05091 rev.*a page 77 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a (equation 1) ts ( r ain + rext ) c ain 9 ts: sampling time r ain : i nput resistance of a/d converter = 1.6 k with 4.5 < avcc < 5.5 ch.1 to ch.5 i nput resistance of a/d converter = 1.4 k with 4.5 < avcc < 5.5 ch.0, ch.6, ch.7 i nput resistance of a/d converter = 2.3 k with 2.7 < avcc < 4.5 ch.1 to ch.5 i nput resistance of a/d converter = 2.0 k with 2.7 < avcc < 4.5 ch . 0, ch.6, ch.7 cain: i nput capacit ance of a/d converter = 9.7 pf with 2.7 < a vcc < 5. 5 rext: output impedance of external circuit (equation 2) tc = tcck 14 tc: compare time tcck : compare clock cycle rext r a in c omparator an xx , analog input pin s c ain analog signal source
document number: 002 - 05091 rev.*a page 78 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a definition s of 1 2 - bit a/d converter t erms ? resolution : analog variation that is recognized by an a/d converter. ? integral nonl inearity : deviation of the line between the zero - transition point (0b000000000000 0b000000000001) and the full - scale transition point (0b111111111110 0b111111111111) from the actual conversion characteristics. ? differential non linearity : deviatio n from the ideal value of the input voltage that is required to change the output code by 1 lsb. *1: at the 32pin product, it is av cc integral nonl inearity of digital output n = v nt - {1lsb (n - 1) + v z t } [lsb] 1lsb differential nonlinearity of digital output n = v (n + 1) t - v nt - 1 [lsb] 1lsb 1lsb = v fst C z t 4094 n : a/d converter digital output value. v z t : voltage at whi ch the digital output ch anges from 0x000 to 0x001. v fst : voltage at whi ch the digital output ch anges from 0xffe to 0xfff. v nt : voltage at whi ch the digital output ch anges from 0x(n ? 1) to 0xn. integral nonl inearity differential non linearity digital output digital output actual conversion characteristics actual conversion characteristics ideal characteristics (actually - measured value) actual conversion characteristics actual conversion characteristics (actually - measured value) (actually - measured value) ideal characteristics (actually - measured value) analog input analog input (actually - measured value) 0x001 0x002 0x003 0x004 0x f fd 0x f fe 0x f ff av ss avrh *1 av ss avrh *1 0x(n - 2) 0x(n - 1) 0x(n+1) 0xn {1 lsb(n - 1) + v zt } v nt v fst v zt v nt v (n+1)t
document number: 002 - 05091 rev.*a page 79 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.6 low - v oltage d etection ch aracteristics 12.6.1 l ow - v oltage d etection r eset (ta = - 40 c to + 105 c ) parameter symbol conditions value unit remarks min typ max detected voltage vdl svhr *1 = 00000 2.25 2.45 2.65 v when voltage drops released voltage vdh 2.30 2.50 2.70 v when voltage rises detected voltage vdl svhr *1 = 00001 2.39 2.60 2.81 v when voltage drops released voltage vdh same as svhr = 00000 value v when voltage rises detected voltage vdl svhr *1 = 00010 2.48 2.70 2.92 v when voltage drops released voltage vdh same as svhr = 0 0000 value v when voltage rises detected voltage vdl svhr *1 = 00011 2.58 2.80 3.02 v when voltage drops released voltage vdh same as svhr = 0 0000 value v when voltage rises detected voltage vdl svhr *1 = 00100 2.76 3.00 3.24 v when voltage drops released voltage vdh same as svhr = 0 0000 value v when voltage rises detected voltage vdl svhr *1 = 00101 2.94 3.20 3.46 v when voltage drops released voltage vdh same as svhr = 0 0000 value v when voltage rises detected voltage vdl svhr *1 = 00110 3.31 3.60 3.89 v when voltage drops released voltage vdh same as svhr = 0 0000 value v when voltage rises detected voltage vdl svhr *1 = 00111 3.40 3.70 4.00 v when voltage drops released voltage vdh same as svhr = 0 0000 value v when voltage rises detected voltage vdl svhr *1 = 01000 3.68 4.00 4.32 v when voltage drops released voltage vdh same as svhr = 0 0000 value v when voltage rises detected voltage vdl svhr *1 = 01001 3.77 4.10 4.43 v when voltage drops released voltage vdh same as svhr = 0 0000 value v when voltage rises detected voltage vdl svhr *1 = 01010 3.86 4.20 4.54 v when voltage drops released voltage vdh same as svhr = 0 0000 value v when voltage rises lvd stabilization wait time t lvdw - - - 8160 t cycp *2 lvd dl - - - 200 cycp indicates the apb 1 bus clock cycle time.
document number: 002 - 05091 rev.*a page 80 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.6.2 l ow - v oltage d etection interrupt (ta = - 40 c to + 105 c ) parameter symbol conditions value uni t remarks min typ max detected voltage vdl svhi = 00011 2.58 2.80 3.02 v when voltage drops released voltage vdh 2.67 2.90 3.13 v when voltage rises detected voltage vdl svhi = 00100 2.76 3.00 3.24 v when voltage drops released voltage vdh 2.85 3.10 3.35 v when voltage rises detected voltage vdl svhi = 00101 2.94 3.20 3.46 v when voltage drops released voltage vdh 3.04 3.30 3.56 v when voltage rises detected voltage vdl svhi = 00110 3.31 3.60 3.89 v when voltage drops released voltage vdh 3.40 3.70 4.00 v when voltage rises detected voltage vdl svhi = 00111 3.40 3 . 70 4.00 v when voltage drops released voltage vdh 3.50 3 . 8 0 4.10 v when voltage rises detected voltage vdl svhi = 01000 3.68 4 . 00 4.32 v when voltage drops released voltage vdh 3.77 4.10 4.43 v when voltage rises detected voltage vdl svhi = 01001 3.77 4 . 10 4.43 v when voltage drops released voltage vdh 3.86 4.20 4.54 v when voltage rises detected voltage vdl svhi = 01010 3.86 4 . 20 4.54 v when voltage drops released voltage vdh 3.96 4. 3 0 4.64 v when voltage rises lvd stabilization wait time t lvdw - - - 8160 t cycp * lvd dl - - - 200 *:t cycp represents the apb 1 bus clock cycle time.
document number: 002 - 05091 rev.*a page 81 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.7 flash memory write/erase ch aracteristics ( v cc = 2.7 v to 5.5 v , ta = - 40 c to + 105 c ) parameter value unit remarks min typ max sector erase time large s ector - 0.7 2.2 s the sector erase time includes the time of writing prior to internal erase. small sector 0.3 0.9 half word (16 - bit) write time - 30 528 w rite /erase cycle and data hold time w rite /e rase cycle data hold time (year ) remarks 1,000 20* 10,000 10* *: th is value was converted from the result of a technology reliability assessment. (this value was converted from the result of a high temperature accelerated test using the arrhenius equation with the average temperature value being + 8 5 c ).
document number: 002 - 05091 rev.*a page 82 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.8 return time from low - power consumption mode 12.8.1 return f actor: interrupt the return time from low - power consumption mode is indicated as follows. it is from receiving the return factor to starting the program operation. return c ount t ime ( v cc = 2.7v to 5.5v , ta = - 40 c to + 105 c ) parameter symbol value * unit remarks typ max sleep mode ticnt t cycc cycc 80 + 17 cycc operation example of return from l ow - p ower consumption mode (by external interrupt*) *: external interrupt is set to detecting fall edge. e x t . i n t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u
document number: 002 - 05091 rev.*a page 83 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a operation example of return from low - power consumption mode (by internal resource interrupt*) *: internal resource interrupt is not included in return factor by the kind of l ow - power consumption mode. notes: ? the return factor is different in each low - power consumption modes. see "chapter: low power consumption mode" and "operations of standby modes" in fm0+ family peripheral manual. ? when interrupt recoveries, the operation mode that cpu recoveries depends on the state before the low - power consumption mode transition. see "chapter: low power consumption mode" in "fm0+ family peripheral manual". i n t e r n a l r e s o u r c e i n t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u
document number: 002 - 05091 rev.*a page 84 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 12.8.2 return f actor: reset the return time from low - power consumption mode is indicated as follows. it is from releasing reset to starting the program operation. return c ount t ime ( v cc = 2.7v to 5.5v , ta = - 40 c to + 105 c ) parameter symbol value unit remarks typ max* sleep mode trcnt 208 378 operation example of return from l ow - p ower consumption mode (by initx) i n i t x t r c n t i n t e r n a l r s t c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e
document number: 002 - 05091 rev.*a page 85 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a operation example of return from low power consumption mode (by internal resource reset*) *: internal resource reset is not included in return factor by the kind of low - power consumption mode. notes: ? the return factor is different in each low - power consumption modes. see "chapter: low power consumption mode" and "operations of standby modes" in fm0+ family peripheral manu al. ? when interrupt recoveries, the operation mode that cpu recoveries depends on the state before the low - power consumption mode transition. see "chapter: low power consumption mode" in "fm0+ family peripheral manual". ? the time during the power - on reset/low - voltage det ection reset is excluded. see " 12.4.7 power - on reset timing " for the detail on the time during the power - on reset/low - voltage detection reset. ? when in recovery from reset, cpu changes to the high - speed cr run mode. when using the main clock or the pll clock, it is necessary to add the main clock oscillatio n stabilization wait time or the main pll clock stabilization wait time. ? the internal resource reset means the watchdog reset and the csv reset. i n t e r n a l r e s o u r c e r s t t r c n t i n t e r n a l r s t c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e
document number: 002 - 05091 rev.*a page 86 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 13. ordering information part number package s6e1a11b0agp2 plastic ? l qfp (0.8 0 mm pitch) , 32 pin s ( fpt - 32p - m30 ) s6e1a12b0agp2 s6e1a11b0agn2 plastic ? qfn (0.5 0 mm pitch) , 32 pin s ( lcc - 32p - m 73 ) S6E1A12B0AGN2 s6e1a11c0agv2 plastic ? l qf p (0.5 0 mm pitch) , 48 pin s ( fpt - 48 p - m 49 ) s6e1a12c0agv2 s6e1a11c0agn2 plastic ? qfn (0.5 0 mm pitch) , 48 pin s ( lcc - 48 p - m 74 ) s6e1a12c0agn2 s6e1a11c0agf2 plastic ? l qfp (0. 6 5 mm pitch) , 5 2 pin s ( fpt - 5 2p - m 02 ) s6e1a12c0agf2
document number: 002 - 05091 rev.*a page 87 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 14. package dimensions
document number: 002 - 05091 rev.*a page 88 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a
document number: 002 - 05091 rev.*a page 89 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 48-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 7.00 mm 7.00 mm lead shape gullwing lead bend direction no rm al bend sealing method plastic mold mounting height 1.70 mm max we ight 0.17 g 48-pin plastic lqfp (fpt-48p-m49) (fpt-48p-m49) c 2010 fujitsu semiconductor limited hmbf48-49sc-1-2 24 13 36 25 48 37 index *7.00 0.10(.276 .004)sq 9.00 0.20(.354 .008)sq 0.145 0.055 (.006 .002) 0.08(.003) "a" 0 ~8 .059 C.004 +.008 C0.10 +0.20 1.50 0.60 0.15 (.024 .006) 0.10 0.10 (.004 .004) (stand off) 0.25(.010) details of "a" part 1 12 0.08(.003) m (.008 .002) 0.22 0.05 0.50(.020) (mounting height) dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
document number: 002 - 05091 rev.*a page 90 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a
document number: 002 - 05091 rev.*a page 91 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a
document number: 002 - 05091 rev.*a page 92 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a 15. major changes spansion p ublication number: s6e1a1_ds710 - 00001 page section change results revision 0.1 - - initial release revision 1.0 [july 16,2014] - - revised from "preliminary" to "full production" 3 1. description revised from "type1" product to "type1 - m0+" product 5 2. features revised "processor version" 6 2. features revised "conversion time" of 12 - bit a/d converter 9 3. product lineup added "note" for accuracy of built - in cr 21,22,23 , 24,25 6. list of pin functions list of pin functions revised pin number 30 and 31 of lqfp - 32 and qfn - 32 23 6. list of pin functions list of pin functions revised function description of sot1_x(sda1_x) 40 12. memory map memory map (1) revised from "mtb resister" to "mtb resister(sfr)" 41 12. memory map memory map (2) revised product name and ram address 46 14. electrical characteristics 14. 1 absolute maximum ratings revised analog pin input voltage 47 14. electrical characteristics 14.2 recommended operating conditions added note " *2" 48,49,50 14. electrical characteristics 14 .3 dc characteristics 14.3.1 current rating ? revised and added "conditions" ? revised the value of "tbd" 52 14. electrical characteristics 14. 4 ac characteristics 14.4.1 main clock input characteristics revised the value of "internal operating clock frequency" and "internal operating clock cycle time" 54 14. electrical characteris tics 14.4 ac characteristics 14.4.3 built - in cr oscillation characteristics revised the value of "tbd" 55 14. electrical characteristics 14.4 ac characteristics 14.4.5 operating conditions of main pll(in the case of using the built - in high - speed cr clock as the input clock of the main pll) ? revised the value of "tbd" ? revised the maximum value of "main pll clock frequency" 56 14. electrical characteristics 14.4 ac characteristics 14.4.7 power - on reset timing ? revised the value of "tbd" ? revised from " lvdl_minimum" to "vdh_minimum" 78 14. electrical characteristics 14.4 ac characteristics 14.4.12 i2c timing ? revised the condition of "noise filter" ? revised the note for noise filter 80 14. electrical characteristics 14.5 12 - bit a/d converter ? revised the value of "conversion time", "sampling time" and "compare clock cycle" ? revised the value of " state transition time to operation permission " ? revised the note 83,84 14. electrical characteristics 14.6 low - voltage detection characteristics re vised the value of svhr and svhi 85 14. electrical characteristics 14.7 flash memory write/erase characteristics ? revised the value of "tbd" ? revised the value of typical
document number: 002 - 05091 rev.*a page 93 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a page section change results 86,88 14. electrical characteristics 14.8 return time from low - power consumption mode revised the value of "tbd" 90 15. ordering information revised from "lcc - 52p - m02" to "fpt - 52p - m02" note: please see document history about later revised information.
document number: 002 - 05091 rev.*a page 94 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a document history document title: s6e1a11b0a/c0a, s6e1a12b0a/c0a 32 - bit arm ? cortex ? - fm0+ based microcontroller document number: 002 - 05091 revision ecn orig. of change submission date description of change ** - akih 07/16/2014 migrated to cypress and assigned document number 002 - 05091. no change to document contents or format. *a 5131394 akih 02/ 1 0/2016 updated to cypress format.
document number: 002 - 05091 rev.*a february 10, 2016 page 95 of 95 s6e1a11b0a/ c0a s6e1a1 2b0a/ c0a sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, visit us at cypress locations . products automotive cypress.com/go/automotive clocks & buffers cypress.com/go/clocks interface cypress.com/go/interface lighting & power control cypress.com/go/powerpsoc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cypress.com/go/touc h usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless spansion products cypress.com/spansionproducts psoc? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support cypress, the cypress logo, spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse tm , ornand tm , easy designsim tm , traveo tm and combinations thereof, are trademarks and registered trademarks of cypress semiconductor corp. arm and cortex are the registered trademarks of arm limited in the eu and other countries. all other trademarks or registered trademarks referenced herein ar e the property of their respective owners. ? cypress semiconductor corporation, 201 4 - 2016 . the information contained herein is subject to change without notice. cypress semiconductor corporation assumes no responsi bility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license und er patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreem ent with cypress. furthermore, cypress does n ot authorize its products for use as critical components in life - support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the in clusion of cypress products in life - support systems application im plies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. this source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and s ubject to worldw ide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non - exclusive, non - transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in supp ort of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or representation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implie d, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to the materials described herein. cypress doe s not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not autho rize its products for use as critical components in life - support systems where a malfunction or failure may reasonably be exp ected to result in significant injury to the user. the inclusion of cypress product in a life - support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limite d by and subject to the applicable cypress software license agreement.

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